Method for improving channel hole uniformity of a three-dimensional memory device
A method for forming a three-dimensional memory device includes disposing a material layer over a substrate, forming a plurality of channel-forming holes and a plurality of sacrificial holes around the plurality of channel-forming holes in an array-forming region of the material layer, and forming a plurality of semiconductor channels based on the channel-forming holes and at least one gate line slit (GLS) based on at least one of the plurality of sacrificial holes. A location of the at least one GLS overlaps with the at least one of the plurality of sacrificial holes.
1. A method for forming a three-dimensional memory device, comprising:
disposing a material layer over a substrate;
forming two adjacent top select gates (TSGs) separated by a TSG-oxide-fill in an array-forming region of the material layer;
after forming the TSG-oxide-fill, forming a plurality of channel-forming holes and a plurality of sacrificial holes in the array-forming region of the material layer, wherein the plurality of sacrificial holes include a first column and a second column of sacrificial holes each located on a different side of the TSG-oxide-fill; and
forming a plurality of semiconductor channels based on the channel-forming holes and at least one gate line slit (GLS) based on at least one of the plurality of sacrificial holes, wherein the at least one GLS includes a wall structure penetrating the material layer and contacting with the substrate, and a location of the at least one GLS overlaps with the at least one of the plurality of sacrificial holes.
2. The method of claim 1 , wherein forming the plurality of channel-forming holes and the plurality of sacrificial holes comprises:
forming a first patterned photoresist layer over the material layer, wherein the first patterned photoresist layer comprises a plurality of channel-forming openings and a plurality of sacrificial openings; and
forming the plurality of channel-forming openings and the plurality of sacrificial openings through the material layer until the substrate is exposed.
3. The method of claim 1 , further comprising locating the plurality of sacrificial holes adjacent to boundaries of the array-forming region.
4. The method of claim 3 , further comprising forming the plurality of channel-forming; holes and the plurality of sacrificial holes to have the same cross-sectional dimensions.
5. The method of claim 4 , further comprising:
arranging the plurality of channel-forming, holes and the plurality of sacrificial holes in an array; and
locating the plurality of channel-forming holes adjacent to the plurality of sacrificial holes.
6. The method of claim 5 , further comprising:
forming the plurality of channel-forming holes and the plurality of sacrificial holes in the array-forming region;
locating the first column and the second column of sacrificial holes that is distributed adjacent to the boundaries of the array-forming region.
7. The method of claim 6 , further comprising:
arranging the first column and the second column of sacrificial holes to be adjacent to a boundary of the array.
8. The method of claim 7 , further comprising forming the plurality of sacrificial holes of the same dimensions as the plurality of channel-forming holes.
9. The method of claim 8 , wherein forming the plurality of semiconductor channels based on the channel-forming holes and the at least one GLS based on the at least one of the plurality of sacrificial holes comprises:
filling the plurality of channel-forming holes with channel-forming layers;
forming a plurality of dielectric filling structures based on the plurality of sacrificial holes;
forming at least one GLS-forming trench to remove the plurality of dielectric filling structures; and
filling the at least one GLS-forming trench with a conductive material.
10. The method of claim 9 , wherein forming the plurality of dielectric filling structures based on the plurality of sacrificial holes comprises:
filling the plurality of sacrificial holes with the channel-forming layers;
removing the channel-forming layers in the plurality of sacrificial holes to form a plurality of dielectric filling holes; and
forming a dielectric filling material in the plurality of dielectric filling holes.
11. The method of claim 10 , wherein forming the dielectric filling material comprises performing a low-temperature spin-on dielectric process.
12. The method of claim 11 , further comprising forming the at least one GLS-forming trench with a projection portion on the substrate that covers a projection of at least one of the plurality of dielectric filling structures on the substrate.
13. The method of claim 12 , further comprising forming two GLS-forming trenches each being located adjacent to a different side of the boundaries of the array-forming region.
14. The method of claim 12 , further comprising forming the at least one GLS-forming trench with a projection portion on the substrate that is greater than the projection of the plurality of dielectric filling structures on the substrate.
15. The method of claim 14 , further comprising forming the dielectric filling material with at least one material that forms the material layer.
16. The method of claim 15 , wherein forming the dielectric filling material comprises forming silicon oxide.
17. The method of claim 16 , further comprising forming the plurality of dielectric tilling holes of dimensions the same as the plurality of sacrificial holes.
18. The method of claim 17 further comprising:
cleaning the plurality of channel-forming holes before filling the plurality of channel-forming holes with the channel-forming layers; and
planarizing the at least one GLS-forming trench after the conductive material is filled therein.
19. The method of claim 1 , wherein the material layer includes at least one of a staircase structure and a dielectric stack.
20. The method of claim 1 , wherein forming the plurality of sacrificial holes further comprises forming a third row of sacrificial holes each penetrating the TSG-oxide-fill.