Semiconductor device with reduced trap defect and method of forming the same

1. A method of manufacturing a semiconductor device, comprising:

providing a substrate comprising a surface;

depositing a first dielectric layer and a second dielectric layer over the substrate;

forming a dummy gate electrode over the second dielectric layer;

forming a gate spacer surrounding the dummy gate electrode;

forming lightly-doped source/drain (LDD) regions in the substrate on two sides of the gate spacer;

forming source/drain regions in the respective LDD regions;

removing the dummy gate electrode to form a replacement gate;

forming an inter-layer dielectric (ILD) layer over the replacement gate and the source/drain regions; and

performing a first treatment by introducing a trap-repairing element into the LDD regions before the forming of the source/drain regions,

wherein the first treatment comprises an ion implantation with a tilted angle between about 10° and about 30°.

2. The method of claim 1 , wherein the trap-repairing element comprises an electronegativity greater than an electronegativity of silicon or oxygen.

3. The method of claim 1 , further comprising performing a thermal operation on the LDD regions at a temperature greater than about 900° C. subsequent to the performing of the first treatment.

4. The method of claim 1 , wherein the trap-repairing element comprises a dopant type opposite to a dopant type of the LDD regions.

5. The method of claim 1 , wherein forming lightly-doped source/drain (LDD) regions comprises performing a first ion implantation at a first power, and wherein introducing the trap-repairing element into the LDD regions comprises performing an second ion implantation at a second power less than the first power.

6. The method of claim 5 , wherein the second power is between about 0.5 KeV and about 2 KeV.

7. The method of claim 1 , wherein the first treatment comprises an ion implantation dose between about 5E14 atoms/cm 2 and about 1.5E15 atoms/cm 2 .

8. The method of claim 1 , wherein forming a dummy gate electrode comprises:

depositing a gate electrode layer over the second dielectric layer; and

patterning the gate electrode layer and the second dielectric layer into the dummy gate electrode subsequent to a second treatment.

9. The method of claim 8 , wherein the second treatment comprises using a nitrogen plasma to introduce nitrogen into the second dielectric layer.

10. The method of claim 9 , wherein using the nitrogen plasma to introduce nitrogen comprises introducing a nitrogen-containing gas with a flow rate between about 10 sccm and about 300 sccm.

11. The method of claim 8 , wherein the first dielectric layer comprises silicon oxide and the second dielectric layer comprises a high-k dielectric material.

12. The method of claim 1 , further comprising:

performing a first annealing operation after the forming of the source/drain regions at a first temperature; and

performing a third treatment subsequent to the first annealing operation at a second temperature less than the first temperature.

13. The method of claim 12 , wherein the third treatment comprises a second annealing operation conducted in hydrogen at a pressure between about 10 atm and about 20 atm.

14. A method of manufacturing a semiconductor device, comprising:

providing a substrate comprising a surface;

depositing a high-k dielectric layer over the substrate;

forming a dummy gate electrode over the high-k dielectric layer;

forming a gate spacer to surround the dummy gate electrode;

forming lightly-doped source/drain (LDD) regions in the substrate on two sides of the gate spacer;

forming source/drain regions in the respective LDD regions;

forming a replacement gate and removing the dummy gate electrode;

forming contact plugs to electrically couple to the replacement gate and the source/drain regions;

performing a trap-repairing operation by introducing a trap repairing element to the LDD regions subsequent to the formation of the LDD regions; and

depositing a dielectric layer over the dummy gate electrode and the LDD regions subsequent to the introducing of the trap-repairing element to the LDD region.

15. The method of claim 14 , wherein the trap-repairing element comprises a dopant type that is same as a dopant type of the LDD regions.

16. The method of claim 14 , wherein the trap-repairing element comprises fluorine.

17. The method of claim 14 , further comprising an annealing operation at a temperature below about 400° C., and the trap-repairing operation is performed after the formation of the replacement gate and a formation of an inter-layer dielectric (ILD) layer over the replacement gate, wherein the contact plugs are formed within the ILD layer.

18. The method of claim 14 , wherein the trap-repairing element comprises an electronegativity greater than an electronegativity of silicon or oxygen.

19. The method of claim 14 , wherein the trap-repairing operation is performed at an RF power between about 0.5 KeV and about 2.0 KeV.

20. A method of manufacturing a semiconductor device, comprising:

providing a semiconductor fin comprising a channel region;

depositing a first dielectric layer and a high-k dielectric layer over the semiconductor fin;

forming a patterned dummy gate over the semiconductor fin subsequent to the depositing of the high-k dielectric layer;

forming a second dielectric layer over the patterned dummy gate and the channel region;

etching a portion of the second dielectric layer contacting the channel region;

forming lightly-doped source/drain (LDD) regions in the semiconductor fin on two sides of the patterned dummy gate;

performing an ion implantation on the LDD regions with an element having an electronegativity greater than electronegativities of silicon or oxygen;

forming source/drain regions in the respective LDD regions;

performing an ion implantation on the source/drain regions;

performing a first annealing operation on the ion-implanted source/drain regions at a first temperature;

forming a replacement gate by etching the patterned dummy gate; and

forming an inter-layer dielectric layer over the source/drain regions and the replacement gate.