Interconnect structure of semiconductor device including barrier layer located entirely in via
Implementations of the present disclosure provide methods for preventing contact damage or oxidation after via/trench opening formation. In one example, the method includes forming an opening in a structure on the substrate to expose a portion of a surface of an electrically conductive feature, and bombarding a surface of a mask layer of the structure using energy species formed from a plasma to release reactive species from the mask layer, wherein the released reactive species form a barrier layer on the exposed surface of the electrically conductive feature.
1. A semiconductor device, comprising:
a substrate including a first dielectric layer and an electrically conductive feature in the first dielectric layer;
a second dielectric layer over the first dielectric layer; and
an interconnect structure in the second dielectric layer and electrically coupled to the electrically conductive feature, the interconnect structure comprising a barrier layer and a conductive fill, the barrier layer being interposed between the conductive fill and the second dielectric layer, the interconnect structure comprising a line and a via extending from the line to the electrically conductive feature, the barrier layer being located entirely in the via, wherein the via has a sidewall and a bottom, and a ratio of an inner width of the bottom of the via to an inner width of a top of the via is greater than about 33%.
2. The semiconductor device of claim 1 , wherein an angle between the sidewall of the via and a top surface of the first dielectric layer is about 55° to about 75°.
3. The semiconductor device of claim 2 , wherein the angle is about 59.7°.
4. The semiconductor device of claim 1 , wherein the barrier layer comprises a transition metal compound.
5. The semiconductor device of claim 4 , wherein the transition metal compound is titanium nitride (TiN).
6. The semiconductor device of claim 1 , wherein an upper corner of the via has a smooth and rounded profile.
7. A semiconductor device comprising:
a substrate;
a first dielectric layer on the substrate;
a first conductive feature extending through the first dielectric layer;
an etch stop layer (ESL) over the first dielectric layer and the first conductive feature;
a second dielectric layer on the ESL; and
a second conductive feature extending through the second dielectric layer and into the ESL, the second conductive feature comprising a line and a via extending from the line towards the first conductive feature, the via comprising a barrier layer disposed between the first conductive feature and a portion of the second conductive feature above the barrier layer, the barrier layer being located entirely in the via, a first portion of the barrier layer covering a bottom surface of the second conductive feature, a second portion of the barrier layer covering lower sidewalls of the second conductive feature, a ratio of a first thickness of the first portion to a second thickness of the second portion being in a range of 1:0.01 to 1:0.3.
8. The semiconductor device of claim 7 , wherein the barrier layer comprises titanium nitride (TiN), tungsten nitride (WN), or tantalum nitride (TaN).
9. The semiconductor device of claim 7 , wherein the first thickness of the barrier layer is in a range of 20 Angstroms to 8 o Angstroms.
10. The semiconductor device of claim 7 , wherein the ESL comprises two or more layers of different materials selected from the group consisting of silicon nitride, silicon carbide, silicon oxycarbide, nitrogen-doped silicon carbide, silicon oxynitride, silicon oxide hafnium oxide, and aluminum oxide.
11. The semiconductor device of claim 7 , wherein the via has a height dimension in a range of 200 Angstroms to 800 Angstroms.
12. The semiconductor device of claim 7 , wherein the via has an aspect ratio in a range of 10:1 to 30:1.
13. A semiconductor device, comprising:
a substrate;
a conductive feature on the substrate;
a first dielectric layer surrounding the conductive feature;
a second dielectric layer over the conductive feature and the first dielectric layer;
an etch stop layer (ESL) between the first dielectric layer and the second dielectric layer; and
a multi-level interconnect structure in the second dielectric layer and in the ESL, the multi-level interconnect structure comprising a line and a via extending from the line towards the conductive feature, the via fully containing a barrier layer, the barrier layer physically contacting a top surface of the conductive feature, the barrier layer comprising a transition metal nitride.
14. The semiconductor device of claim 13 , wherein a first portion of the barrier layer covers a bottom surface of the via, a second portion of the barrier layer covers lower sidewalls of the via, and a ratio of a first thickness of the first portion to a second thickness of the second portion being in a range of 1:0.1 to 1:0.2.
15. The semiconductor device of claim 13 further comprising an anti-reflective coating (ARC) layer over the second dielectric layer.
16. The semiconductor device of claim 15 , wherein the ARC is a substantially nitrogen-free material.
17. The semiconductor device of claim 16 , wherein the ARC is silicon oxycarbide.
18. The semiconductor device of claim 1 , wherein a first portion of the barrier layer in the bottom of the via has a first thickness, a second portion of the barrier layer in the sidewall of the via has a second thickness, and a ratio of the first thickness to the second thickness is in a range of 1:0.1 to 1:0.2.
19. The semiconductor device of claim 7 , wherein the barrier layer is titanium nitride.
20. The semiconductor device of claim 7 , wherein the barrier layer has a thickness of about 50 Angstroms.