IP Library Granted Patent US 11,335,737
Granted Patent B2
US 11,335,737 · App. 17/002,664 · Granted May 17, 2022

Display device

Inventors: Yeon Tae Kim (Yongin-si, KR); Chung Yi (Seongnam-si, KR); Young Kwan Kim (Seoul, KR); Young Soo No (Seoul, KR)
Assignee: Samsung Display Co., Ltd.
H01L27/3223H01L27/323H01L27/3258H01L27/3262H01L27/3276
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Quick Facts
Patent No.
US 11,335,737
App. No.
17/002,664
Granted
May 17, 2022
Kind
B2
Abstract

A display device includes a display unit including transistors disposed in a display area and signal lines arranged in a non-display area located along an edge of the display area, at least one of the signal lines being electrically connected to the transistors; and an input sensing unit disposed over the display unit and including sensing electrodes disposed on the display area, sensing lines arranged on the non-display area, and a first dummy pattern disposed on the non-display area and spaced apart from the sensing electrodes as compared with the sensing line, wherein the first dummy pattern overlaps a first signal line of the signal lines, the first signal line being spaced farthest from the display area, a planar shape of an overlap pattern formed by overlapping the first dummy pattern and the first signal line coincides with a planar shape of an alignment mark.

Claims (54)

1. A display device, comprising:

a display unit comprising transistors disposed in a display area, signal lines arranged in a non-display area located along an edge of the display area, and a first dummy line pattern disposed in the non-display area and spaced apart from the display area, at least one of the signal lines being electrically connected to the transistors; and

an input sensing unit disposed over the display unit, the input sensing unit comprising sensing electrodes disposed on the display area and sensing lines arranged on the non-display area, at least one of the sensing lines being electrically connected to the sensing electrodes,

wherein:

the first dummy line pattern overlaps a first sensing line of the sensing lines, the first sensing line being spaced farthest from the display area;

a planar shape of an overlap pattern formed by overlapping the first dummy line pattern and the first sensing line coincides with a planar shape of an alignment mark;

the alignment mark comprises a first portion having a first area and a second portion having a second area and protruding from the first portion; and

a planar shape of a non-overlap portion of the first dummy line pattern that does not overlap the first sensing line, is the same as a planar shape of the second portion of the alignment mark.

2. The display device of claim 1 , wherein the first dummy line pattern is isolated from the signal lines and the sensing lines.

3. The display device of claim 1 , wherein the first sensing line is extended along an edge of the input sensing unit.

4. The display device of claim 1 , wherein

each of the transistors comprises:

a semiconductor layer comprising a channel;

a first conductive layer disposed on the semiconductor layer and comprising a gate electrode; and

a second conductive layer disposed on the first conductive layer and comprising a source electrode and a drain electrode; and

wherein the first conductive layer comprises the first dummy line pattern.

5. The display device of claim 1 , wherein

each of the transistors comprises:

a semiconductor layer comprising a channel;

a first conductive layer disposed on the semiconductor layer and comprising a gate electrode; and

a second conductive layer disposed on the first conductive layer and comprising a source electrode and a drain electrode; and

wherein the second conductive layer comprises the first dummy line pattern.

6. The display device of claim 5 , wherein:

the display unit further comprises a second dummy line pattern disposed on the non-display area and spaced apart from the display areas;

the second dummy line pattern overlaps the first sensing line;

the alignment mark further comprises a third portion having a third area and protruding from the first portion; and

a planar shape of the overlap pattern further comprises overlapping the first dummy line pattern, the second dummy line pattern, and the first sensing line that coincides with a planar shape of the alignment mark.

7. The display device of claim 1 , wherein:

the input sensing unit further comprises a first dummy pattern disposed on the non-display area and spaced apart from the sensing electrodes;

the first dummy pattern overlaps the first dummy line pattern;

the overlap pattern further comprises overlapping the first dummy pattern, the first dummy line pattern, and the first sensing line;

the first dummy pattern is smaller than the second portion of the alignment mark; and

the first dummy line pattern is smaller than the second portion of the alignment mark.

8. A display device, comprising:

a substrate comprising a display area and a non-display area located at one side of the display area;

a circuit element layer disposed on the substrate, the circuit element layer comprising a transistor overlapping the display area, signal lines disposed on the non-display area, and a first dummy line pattern, at least one of the signal lines being electrically connected to the transistor; and

a display element layer disposed on the display area, the display element layer comprising a light emitting element overlapping the display area and electrically connected to the transistor,

wherein:

the first dummy line pattern overlaps a first signal line of the signal lines, spaced farthest from the display area, in a thickness direction of the substrate, and is isolated from the first signal line;

a planar shape of an overlap pattern formed by overlapping the first dummy line pattern and the first signal line coincides with a planar shape of an alignment mark;

the alignment mark comprises a first portion having a first area and a second portion having a second area and protruding from the first portion; and

a planar shape of a non-overlap portion of the first dummy line pattern that does not overlap the first signal line, is the same as a planar shape of the second portion of the alignment mark.

9. The display device of claim 8 , wherein the circuit element layer comprises:

a semiconductor layer disposed on the display area of the substrate;

a first insulating layer disposed on the semiconductor layer and the substrate;

a first conductive layer disposed on the first insulating layer and comprising a gate electrode overlapping the semiconductor layer, and the first dummy line pattern;

a second insulating layer disposed on the first conductive layer; and

a second conductive layer disposed on the second insulating layer and comprising a source electrode or a drain electrode overlapping the semiconductor layer, and the signal lines.

10. The display device of claim 8 , wherein the circuit element layer comprises:

a semiconductor layer disposed on the display area of the substrate;

a first insulating layer disposed on the semiconductor layer and the substrate;

a first conductive layer disposed on the first insulating layer and comprising a gate electrode overlapping the semiconductor layer, and the signal lines;

a second insulating layer disposed on the first conductive layer; and

a second conductive layer disposed on the second insulating layer and comprising a source electrode or a drain electrode overlapping the semiconductor layer, and the first dummy line pattern.

Priority Claims (1)
KR 10-2018-0086741 · Jul 25, 2018 · national
Continuity (2)
Division 16299140 · Mar 12, 2019
Related Publication 20210050392A1 · Feb 18, 2021
Cited By (1)
US 12,554,157