IP Library › Granted Patent US 11,335,746
Granted Patent B2
US 11,335,746 · App. 16/743,220 · Granted May 17, 2022

Display device and electronic device

Inventors: Hideaki Shishido (Kanagawa, JP); Naoto Kusumoto (Kanagawa, JP)
H01L27/3246G02F1/13306G06F3/0412G09G3/2092G09G3/3225G09G3/3233G09G3/3258G09G3/3648H01L27/3262H01L27/3267H01L29/7869H01L51/105H01L51/5212G02F2201/44G02F2203/02G06F3/041G06F2203/04103G09G2310/0291H01L27/1225H01L51/0017H01L51/502
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Quick Facts
Patent No.
US 11,335,746
App. No.
16/743,220
Granted
May 17, 2022
Kind
B2
Abstract

A display device with a narrow bezel is provided. The display device includes a pixel circuit and a driver circuit which are provided on the same plane. The driver circuit includes a selection circuit and a buffer circuit. The selection circuit includes a first transistor. The buffer circuit includes a second transistor. The first transistor has a region overlapping with the second transistor. One of a source and a drain of the first transistor is electrically connected to a gate of the second transistor. One of a source and a drain of the second transistor is electrically connected to the pixel circuit.

Claims (27)

1. A display device comprising:

a pixel circuit and a driver circuit over a substrate,

wherein the driver circuit includes a shift register circuit and a buffer circuit,

wherein the shift register circuit includes a first transistor,

wherein the buffer circuit includes a second transistor,

wherein the shift register circuit is provided over the buffer circuit,

wherein the first transistor has a same conductivity type as the second transistor,

wherein one of a source and a drain of the first transistor is electrically connected to a gate of the second transistor, and

wherein a channel length direction of the first transistor is not in parallel with a channel length direction of the second transistor.

2. The display device according to claim 1 , wherein the driver circuit is a gate driver.

3. The display device according to claim 1 , further comprising a planarization film between the shift register circuit and the buffer circuit.

4. The display device according to claim 1 , wherein channel formation regions of the plurality of first transistors and the plurality of second transistors include a metal oxide.

5. An electronic device comprising a touch sensor overlapping with the display device, and the display device according to claim 1 .

6. A display device comprising:

a pixel circuit and a driver circuit over a substrate,

wherein the driver circuit includes a shift register circuit and a buffer circuit,

wherein the shift register circuit includes a first transistor,

wherein the buffer circuit includes a second transistor,

wherein the shift register circuit is provided over the buffer circuit,

wherein a width of the buffer circuit is larger than a width of the shift register circuit,

wherein the first transistor has a same conductivity type as the second transistor,

wherein one of a source and a drain of the first transistor is electrically connected to a gate of the second transistor, and

wherein a channel length direction of the first transistor is not in parallel with a channel length direction of the second transistor.

7. The display device according to claim 6 , wherein the driver circuit is a gate driver.

8. The display device according to claim 6 , further comprising a planarization film between the shift register circuit and the buffer circuit.

9. The display device according to claim 6 , wherein channel formation regions of the plurality of first transistors and the plurality of second transistors include a metal oxide.

10. An electronic device comprising a touch sensor overlapping with the display device, and the display device according to claim 6 .

Priority Claims (1)
JP JP2016-142898 · Jul 21, 2016 · national
Continuity (2)
Continuation 15654108 · Jul 19, 2017
Related Publication 20200152897A1 · May 14, 2020