IP Library › Granted Patent US 11,340,960

Granted Patent B2

US 11,340,960 · App. 16/833,454 · Granted May 24, 2022

Apparatuses, methods, and systems for hardware-assisted lockstep of processor cores

Inventors: Umberto Santoni (Scottsdale, AZ); Philip Abraham (Burlingame, CA)

Assignee: Intel Corporation

G06F9/52 G06F9/3005 G06F9/30101 G06F9/30196 G06F9/3842 G06F11/16 G06F11/1629

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Quick Facts

Patent No.: US 11,340,960
App. No.: 16/833,454
Granted: May 24, 2022
Kind: B2

External Links

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Abstract

Systems, methods, and apparatuses relating to circuitry to implement lockstep of processor cores are described. In one embodiment, a hardware processor comprises a first processor core comprising a first control flow signature register and a first execution circuit, a second processor core comprising a second control flow signature register and a second execution circuit, and at least one signature circuit to perform a first state history compression operation on a first instruction that executes on the first execution circuit of the first processor core to produce a first result, store the first result in the first control flow signature register, perform a second state history compression operation on a second instruction that executes on the second execution circuit of the second processor core to produce a second result, and store the second result in the second control flow signature register.

Claims (99)

1. A hardware processor comprising:

a first processor core comprising a first control flow signature register and a first execution circuit;

a second processor core comprising a second control flow signature register and a second execution circuit; and

at least one signature circuit to:

perform a first state history compression operation on a first instruction that executes on the first execution circuit of the first processor core to produce a first result,

store the first result in the first control flow signature register,

perform a second state history compression operation on a second instruction that executes on the second execution circuit of the second processor core to produce a second result, and

store the second result in the second control flow signature register.

2. The hardware processor of claim 1 , wherein the at least one signature circuit is to:

perform a third state history compression operation on a third instruction that executes on the first execution circuit of the first processor core to produce a third result,

perform a fourth state history compression operation on the first result and the third result to produce a fourth result,

store the fourth result in the first control flow signature register,

perform a fifth state history compression operation on a fourth instruction that executes on the second execution circuit of the second processor core to produce a fifth result,

perform a sixth state history compression operation on the second result and the fifth result to produce a sixth result, and

store the sixth result in the second control flow signature register.

3. The hardware processor of claim 1 , wherein the first state history compression operation is performed on an opcode and an operand of the first instruction.

4. The hardware processor of claim 1 , further comprising decoding an instruction with a decoder of the first processor core into a decoded instruction and executing the decoded instruction with the first execution circuit of the first processor core to compare the first result in the first control flow signature register and the second result in the second control flow signature register, and trigger an error indication when the first result differs from the second result.

5. The hardware processor of claim 1 , wherein the first processor core comprises a first data flow signature register, the second processor core comprises a second data flow signature register, and the at least one signature circuit is to:

perform a third state history compression operation on a resultant of the first instruction that executes on the first execution circuit of the first processor core to produce a third result,

store the third result in the first data flow signature register,

perform a fourth state history compression operation on a resultant of the second instruction that executes on the second execution circuit of the second processor core to produce a fourth result, and

store the fourth result in the second data flow signature register.

6. The hardware processor of claim 5 , further comprising decoding an instruction with a decoder of the first processor core into a decoded instruction and executing the decoded instruction with the first execution circuit of the first processor core to compare the first result in the first control flow signature register and the second result in the second control flow signature register, compare the third result in the first data flow signature register and the fourth result in the second data flow signature register, and trigger an error indication when the first result differs from the second result or when the third result differs from the fourth result.

7. The hardware processor of claim 5 , wherein the at least one signature circuit is to:

perform a fifth state history compression operation on a resultant of a third instruction that executes on the first execution circuit of the first processor core to produce a fifth result,

perform a sixth state history compression operation on the third result and the fifth result to produce a sixth result,

store the sixth result in the first data flow signature register,

perform a seventh state history compression operation on a resultant of a fourth instruction that executes on the second execution circuit of the second processor core to produce a seventh result,

perform an eighth state history compression operation on the fourth result and the seventh result to produce an eighth result, and

store the eighth result in the second data flow signature register.

8. The hardware processor of claim 1 , wherein the first state history compression operation on the first instruction comprises a first cyclic redundancy check on an instruction pointer of the first instruction and a second cyclic redundancy check on at least one field of the first instruction to produce the first result.

9. A method comprising:

executing a first instruction with a first execution circuit of a first processor core of a processor;

performing a first state history compression operation on the first instruction that executes on the first execution circuit of the first processor core to produce a first result;

storing the first result in a first control flow signature register of the first processor core;

executing a second instruction with a second execution circuit of a second processor core of the processor;

performing a second state history compression operation on the second instruction that executes on the second execution circuit of the second processor core to produce a second result; and

storing the second result in a second control flow signature register of the second processor core.

10. The method of claim 9 , further comprising:

performing a third state history compression operation on a third instruction that executes on the first execution circuit of the first processor core to produce a third result;

performing a fourth state history compression operation on the first result and the third result to produce a fourth result;

storing the fourth result in the first control flow signature register;

performing a fifth state history compression operation on a fourth instruction that executes on the second execution circuit of the second processor core to produce a fifth result;

performing a sixth state history compression operation on the second result and the fifth result to produce a sixth result; and

storing the sixth result in the second control flow signature register.

11. The method of claim 9 , wherein the first state history compression operation is performed on an opcode and an operand of the first instruction.

12. The method of claim 9 , further comprising:

decoding an instruction with a decoder of the first processor core into a decoded instruction; and

13. The method of claim 9 , further comprising:

performing a third state history compression operation on a resultant of the first instruction that executes on the first execution circuit of the first processor core to produce a third result,

storing the third result in a first data flow signature register of the first processor core;

performing a fourth state history compression operation on a resultant of the second instruction that executes on the second execution circuit of the second processor core to produce a fourth result; and

storing the fourth result in a second data flow signature register of the second processor core.

14. The method of claim 13 , further comprising:

decoding an instruction with a decoder of the first processor core into a decoded instruction; and

executing the decoded instruction with the first execution circuit of the first processor core to compare the first result in the first control flow signature register and the second result in the second control flow signature register, compare the third result in the first data flow signature register and the fourth result in the second data flow signature register, and trigger an error indication when the first result differs from the second result or when the third result differs from the fourth result.

15. The method of claim 13 , further comprising:

performing a fifth state history compression operation on a resultant of a third instruction that executes on the first execution circuit of the first processor core to produce a fifth result;

performing a sixth state history compression operation on the third result and the fifth result to produce a sixth result;

storing the sixth result in the first data flow signature register;

performing a seventh state history compression operation on a resultant of a fourth instruction that executes on the second execution circuit of the second processor core to produce a seventh result;

performing an eighth state history compression operation on the fourth result and the seventh result to produce an eighth result; and

storing the eighth result in the second data flow signature register.

16. The method of claim 9 , wherein the performing the first state history compression operation on the first instruction comprises performing a first cyclic redundancy check on an instruction pointer of the first instruction and a second cyclic redundancy check on at least one field of the first instruction to produce the first result.

17. A non-transitory machine readable medium that stores program code that when executed by a machine causes the machine to perform a method comprising:

executing a first instruction with a first execution circuit of a first processor core of a processor;

performing a first state history compression operation on the first instruction that executes on the first execution circuit of the first processor core to produce a first result;

storing the first result in a first control flow signature register of the first processor core;

executing a second instruction with a second execution circuit of a second processor core of the processor;

performing a second state history compression operation on the second instruction that executes on the second execution circuit of the second processor core to produce a second result; and

storing the second result in a second control flow signature register of the second processor core.

18. The non-transitory machine readable medium of claim 17 , wherein the method further comprises:

performing a third state history compression operation on a third instruction that executes on the first execution circuit of the first processor core to produce a third result;

performing a fourth state history compression operation on the first result and the third result to produce a fourth result;

storing the fourth result in the first control flow signature register;

performing a fifth state history compression operation on a fourth instruction that executes on the second execution circuit of the second processor core to produce a fifth result;

performing a sixth state history compression operation on the second result and the fifth result to produce a sixth result; and

storing the sixth result in the second control flow signature register.

19. The non-transitory machine readable medium of claim 17 , wherein the first state history compression operation is performed on an opcode and an operand of the first instruction.

20. The non-transitory machine readable medium of claim 17 , wherein the method further comprises:

decoding an instruction with a decoder of the first processor core into a decoded instruction; and

21. The non-transitory machine readable medium of claim 17 , wherein the method further comprises:

performing a third state history compression operation on a resultant of the first instruction that executes on the first execution circuit of the first processor core to produce a third result,

storing the third result in a first data flow signature register of the first processor core;

storing the fourth result in a second data flow signature register of the second processor core.

22. The non-transitory machine readable medium of claim 21 , wherein the method further comprises:

decoding an instruction with a decoder of the first processor core into a decoded instruction; and

23. The non-transitory machine readable medium of claim 21 , wherein the method further comprises:

performing a fifth state history compression operation on a resultant of a third instruction that executes on the first execution circuit of the first processor core to produce a fifth result;

performing a sixth state history compression operation on the third result and the fifth result to produce a sixth result;

storing the sixth result in the first data flow signature register;

performing a seventh state history compression operation on a resultant of a fourth instruction that executes on the second execution circuit of the second processor core to produce a seventh result;

performing an eighth state history compression operation on the fourth result and the seventh result to produce an eighth result; and

storing the eighth result in the second data flow signature register.

24. The non-transitory machine readable medium of claim 17 , wherein the performing the first state history compression operation on the first instruction comprises performing a first cyclic redundancy check on an instruction pointer of the first instruction and a second cyclic redundancy check on at least one field of the first instruction to produce the first result.

Assignments (1)

ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 6, 2020

From: SANTONI, UMBERTO; ABRAHAM, PHILIP

To: INTEL CORPORATION

Reel/Frame 052325/0282 →

Continuity (1)

Related Publication 20210303372A1 · Sep 30, 2021

Cited By (1)

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