System monitor

1. A circuit, comprising:

a microcontroller;

a communication bridge coupled to the microcontroller and configured to implement a state machine comprising:

a first state configured to receive a data frame comprising data;

a second state configured to determine whether a system fault is indicated in the data frame, wherein the first state transitions to the second state when the data frame is received;

a third state configured to assert a fault signal when the system fault is indicated in the data frame, wherein the second states to the third state when the system fault is indicated in the data frame; and

a fourth state configured to transmit the data from the data frame to the microcontroller, wherein the third state transitions to the fourth state after asserting the fault signal;

a power management component coupled to the microcontroller and the communication bridge; and

wherein the communication bridge is configured to implement a second state machine comprising:

a fifth state configured to monitor for the system fault when the microcontroller is in a reduced-power state;

a sixth state configured to assert a trigger signal and transmit the trigger signal to the power management component, wherein the trigger signal causes the power management component to remove the microcontroller from the reduced-power state, and wherein the fifth state transition to the sixth state when the communication bridge determines that a fault exists; and

a seventh state configured to assert the fault signal, wherein the sixth state transitions to the seventh state after asserting the trigger signal.

2. The circuit of claim 1 , wherein the communication bridge transmits the fault signal to the microcontroller.

3. The circuit of claim 1 , wherein the system fault is indicated in a start of frame bit of the data frame.

4. The circuit of claim 3 , wherein the system fault is indicated in start of frame bits of a plurality of bytes of the data frame.

5. The circuit of claim 4 , wherein the system fault is indicated in the data frame when a majority of the start of frame bits of the plurality of bytes of the data frame is asserted.

6. The circuit of claim 1 , wherein the communication bridge determines that the fault exists when the communication bridge detects a fault, receives a fault tone, or does not receive a heartbeat tone for a predetermined period of time.

7. A circuit, comprising:

a register; and

a monitoring circuit coupled to the register and configured to implement a state machine comprising:

a first state configured to generate a data frame including at least some data from the register;

a second state configured to determine a system fault status, wherein the first state transitions to the second state after generating the data frame;

a third state configured to set a fault status indication of the data frame when a fault exists in the system, wherein the second state transitions to the third state when the monitoring circuit detects a fault; and

a fourth state configured to transmit the data frame to a next device, wherein the second state transitions to the fourth state when the monitoring circuit does not detect a fault, and wherein the third state transitions to the fourth state after setting the fault status indication of the data frame;

a fifth state configured to monitor for the fault;

a sixth state configured to generate and transmit a fault tone, wherein the fifth state transition to the sixth state when the monitoring circuit determines that a fault exists; and

a seventh state configured to generate and transmit a heartbeat tone, wherein the fifth state transitions to the seventh state when the monitoring circuit determines that no fault exists.

8. The circuit of claim 7 , wherein the fault status is indicated in a start of frame bit of the data frame.

9. The circuit of claim 8 , wherein the fault status is indicated in start of frame bits of a plurality of bytes of the data frame.

10. The circuit of claim 9 , wherein the fault status is indicated in the data frame when a majority of the start of frame bits of the plurality of bytes of the data frame is asserted.

11. The circuit of claim 7 , wherein the monitoring circuit is configured to transmit the data frame to a communication controller that detects the fault status indication and generates a fault signal in response to detection of the fault status indication.

12. The circuit of claim 7 , wherein the monitoring circuit generates and transmits the fault tone when the monitoring circuit detects a fault, receives a fault tone, or does not receive a heartbeat tone for a predetermined period of time.

13. A system, comprising:

a microcontroller;

a monitoring circuit adapted to be coupled to an energy storage element and configured to:

determine whether a fault associated with the energy storage element is present;

generate a fault tone indicative of the fault when the fault with the energy storage element is present; and

transmit the fault tone; and

a communication bridge connected to the microcontroller and configured to:

receive the indication of the fault; and

assert a fault signal and transmit the fault signal to the microcontroller; and

wherein the communication bridge is in a reduced power mode and the fault tone wakes the communication bridge to cause the communication bridge to assert the fault signal and a trigger signal.

14. The system of claim 13 , wherein the microcontroller is in a reduced power mode, and wherein the trigger signal causes the microcontroller to wake from the reduced power mode.

15. The system of claim 13 , wherein the indication of the fault is a plurality of start of frame bits of a communication frame being asserted, and wherein the communication frame is generated by the monitoring circuit and includes data for transmission to the microcontroller from the monitoring circuit.