Victim cache with write miss merging

1. A caching system comprising:

a first sub-cache;

a second sub-cache, coupled in parallel with the first sub-cache, for storing cache data evicted from the first sub-cache and data associated with write-memory commands that correspond to a miss in the first sub-cache; and

a cache controller configured to:

receive two or more cache commands;

determine a conflict exists between the received two or more cache commands;

determine a conflict resolution between the received two or more cache commands; and

provide the two or more cache commands to the first sub-cache and the second sub-cache.

2. The caching system of claim 1 , wherein the two or more cache commands include a read command and wherein the cache controller is further configured to:

determine, based on a memory address of the read command, that the memory address corresponds to a miss in the first sub-cache;

determine, based on the memory address, that the memory address is associated with a write-memory command cached by the second sub-cache; and

stall the read command until the write-memory command is drained from the second sub-cache.

3. The caching system of claim 1 , wherein the cache controller is further configured to receive the two or more cache commands in parallel.

4. The caching system of claim 3 , wherein the two or more cache commands include a read command and a first write command, and wherein the cache controller is further configured to:

determine, based on a first memory address of the read command, a first cache location in the first sub-cache;

determine that the first memory address corresponds to a miss in the first sub-cache at the first cache location;

receive a second cache location in the second sub-cache associated with the read command;

determine, based on a second memory address of the first write command, that the second memory address is associated with a second write command cached by the second sub-cache at the second cache location;

receive a third cache location in the second sub-cache associated with the first write command; and

evict a cached memory item from the first cache location in the first sub-cache to the third cache location in the second sub-cache.

5. The caching system of claim 3 , wherein the two or more cache commands include a read command and a write command, and wherein the cache controller is further configured to:

determine, based on a first memory address of the read command, a first cache location in the first sub-cache;

determine that the first memory address corresponds to a miss in the first sub-cache at the first cache location;

determine, based on a second memory address of the write command, that the second memory address is stored at the first cache location in the first sub-cache;

stall the read command;

perform the write command;

evict the performed write command to the second sub-cache; and

resume the read command after the eviction.

6. The caching system of claim 3 , wherein the two or more cache commands include a first write command and a second write command, and wherein the cache controller is further configured to:

determine that a first memory address of the first write command corresponds to a miss in the first sub-cache;

determine that a second memory address of the second write command corresponds to a miss in the first sub-cache;

determine that the first memory address and the second memory address match;

merge the first write command and the second write command to produce a merged write command; and

cache the merged write command using the second sub-cache.

7. The caching system of claim 3 , wherein the two or more cache commands include a read command and a write command, and wherein the cache controller is further configured to:

determine that a first memory address of the read command is associated with a hit in the first sub-cache;

determine that a second memory address of the write command is associated with a hit in the first sub-cache;

determine that the first memory address and the second memory address match;

stall the write command until the read command is completed; and

resume the write command.

8. A method for caching data, comprising:

receiving two or more cache commands;

determining a conflict exists between the two or more cache commands;

determining a conflict resolution between the received two or more cache commands; and

providing the two or more cache commands to a first sub-cache and a second sub-cache, wherein the second sub-cache is configured to store, in parallel with the first sub-cache, cache data evicted from the first sub-cache and data associated with write-memory commands that correspond to a miss in the first sub-cache.

9. The method of claim 8 , wherein the two or more cache commands include a read command, the method further comprising:

determining, based on a memory address of the read command, that the memory address corresponds to a miss in the first sub-cache;

determining, based on the memory address, that the memory address is associated with a write-memory command cached by the second sub-cache; and

stalling the read command until the write-memory command is drained from the second sub-cache.

10. The method of claim 8 , wherein the two or more cache commands are received in parallel.

11. The method of claim 10 , wherein the two or more cache commands include a read command and a first write command, the method further comprising:

determining, based on a first memory address of the read command, a first cache location in the first sub-cache;

determining that the first memory address corresponds to a miss in the first sub-cache at the first cache location;

receiving a second cache location in the second sub-cache associated with the read command;

determining, based on a second memory address of the first write command, that the second memory address is associated with a second write command cached by the second sub-cache at the second cache location;

receiving a third cache location in the second sub-cache associated with the first write command; and

evicting a cached memory item from the first cache location in the first sub-cache to the third cache location in the second sub-cache.

12. The method of claim 10 , wherein the two or more cache commands include a read command and a write command, the method further comprising:

determining, based on a first memory address of the read command, a first cache location in the first sub-cache;

determining that the first memory address corresponds to a miss in the first sub-cache at the first cache location;

determining, based on a second memory address of the write command, that the second memory address is stored at the first cache location in the first sub-cache;

stalling the read command;

performing the write command;

evicting the performed write command to the second sub-cache; and

resuming the read command after the eviction.

13. The method of claim 10 , wherein the two or more cache commands include a first write command and a second write command, and wherein the cache controller is further configured to:

determining that a first memory address of the first write command corresponds to a miss in the first sub-cache;

determining that a second memory address of the second write command corresponds to a miss in the first sub-cache;

determining that the first memory address and the second memory address match;

merging the first write command and the second write command to a produce a merged write command; and

caching the merged write command using the second sub-cache.

14. The method of claim 10 , wherein the two or more cache commands include a read command and a write command, the method further comprising:

determining that a first memory address of the read command is cached in the first sub-cache;

determining that a second memory address of the write command is cached in the first sub-cache;

determining that the first memory address and the second memory address match;

stalling the write command until the read command is completed; and

resuming the write command.

15. A device comprising:

a processor;

a first sub-cache; and

a second sub-cache coupled in parallel with the first sub-cache, for storing cache data evicted from the first sub-cache and data associated with write-memory commands that correspond to a miss in the first sub-cache; and

a cache controller configured to:

receive two or more cache commands;

determine a conflict exists between the received two or more cache commands;

determine a conflict resolution between the received two or more cache commands; and

provide the two or more cache commands to the first sub-cache and the second sub-cache.

16. The device of claim 15 , wherein the two or more cache commands include a read command and wherein the cache controller is further configured to:

determine, based on a memory address of the read command, that the memory address corresponds to a miss in the first sub-cache;

determine, based on the memory address, that the memory address is associated with a write-memory command cached by the second sub-cache; and

stall the read command until the write-memory command is drained from the second sub-cache.

17. The device of claim 15 , wherein the cache controller is further configured to receive the two or more cache commands in parallel.

18. The device of claim 17 , wherein the two or more cache commands include a read command and a first write command, and wherein the cache controller is further configured to:

determine, based on a first memory address of the read command, a first cache location in the first sub-cache;

determine that the first memory address corresponds to a miss in the first sub-cache at the first cache location;

receive a second cache location in the second sub-cache associated with the read command;

determine, based on a second memory address of the first write command, that the second memory address is associated with a second write command cached by the second sub-cache at the second cache location;

receive a third cache location in the second sub-cache associated with the first write command; and

evict a cached memory item from the first cache location in the first sub-cache to the third cache location in the second sub-cache.

19. The device of claim 17 , wherein the two or more cache commands include a read command and a write command, and wherein the cache controller is further configured to:

determine, based on a first memory address of the read command, a first cache location in the first sub-cache;

determine that the first memory address corresponds to a miss in the first sub-cache at the first cache location;

determine, based on a second memory address of the write command, that the second memory address is stored at the first cache location in the first sub-cache;

stall the read command;

perform the write command;

evict the performed write command to the second sub-cache; and

resume the read command after the eviction.

20. The device of claim 17 , wherein the two or more cache commands include a first write command and a second write command, and wherein the cache controller is further configured to:

determine that a first memory address of the first write command corresponds to a miss in the first sub-cache;

determine that a second memory address of the second write command corresponds to a miss in the first sub-cache;

determine that the first memory address and the second memory address match;

merge the first write command and the second write command to produce a merged write command; and

cache the merged write command using the second sub-cache.