Reduce well dopant loss in FinFETs through co-implantation
A method of forming a semiconductor device includes performing a first implantation process on a semiconductor substrate to form a deep p-well region, performing a second implantation process on the semiconductor substrate with a diffusion-retarding element to form a co-implantation region, and performing a third implantation process on the semiconductor substrate to form a shallow p-well region over the deep p-well region. The co-implantation region is spaced apart from a top surface of the semiconductor substrate by a portion of the shallow p-well region, and the deep-well region and the shallow p-well region are joined with each other. An n-type Fin Field-Effect Transistor (FinFET) is formed, with the deep p-well region and the shallow p-well region acting as a well region of the n-type FinFET.
1. A semiconductor device comprising:
a bulk semiconductor substrate;
a first isolation region and a second isolation region overlapping the bulk semiconductor substrate;
a first sub-fin between and contacting edges of the first isolation region and the second isolation region;
a first protruding fin overlapping the first sub-fin, wherein the first protruding fin is higher than top surfaces of the first isolation region and the second isolation region;
a p-well region extending into the first sub-fin and the first protruding fin; and
a co-implantation region comprising carbon therein, wherein the co-implantation region comprises:
a first portion extending into the first sub-fin, with a top surface of the first portion being level with or lower than a top surface of the first isolation region; and
a second portion lower than the first isolation region.
2. The semiconductor device of claim 1 , wherein the second portion comprises a part overlapped by a portion of the second isolation region.
3. The semiconductor device of claim 1 further comprising an n-well region comprising a lower portion extending into the bulk semiconductor substrate, wherein the lower portion of the n-well region has a first edge contacting a second edge of the p-well region, and wherein the second portion of the co-implantation region further extends into the lower portion of the n-well region.
4. The semiconductor device of claim 1 further comprising:
a second sub-fin contacting an edge of the second isolation region, wherein the second sub-fin is free from carbon-containing co-implantation region therein;
a second protruding fin overlapping the second sub-fin; and
an n-well region extending into both of the second sub-fin and the second protruding fin.
5. The semiconductor device of claim 1 , wherein the top surface of the first portion of the co-implantation region is substantially level with the top surface of the first isolation region.
6. The semiconductor device of claim 1 , wherein the top surface of the first portion of the co-implantation region is lower than the top surface of the first isolation region.
7. The semiconductor device of claim 1 further comprising an anti-punch-through region in the co-implantation region, wherein the anti-punch-through region has a first p-type impurity concentration higher than a second p-type impurity concentration in portions of the p-well region overlying and underlying the anti-punch-through region.
8. The semiconductor device of claim 1 , wherein the co-implantation region has a carbon concentration in a range between about 1×10 17 /cm 3 and about 1×10 19 /cm 3 .
9. A semiconductor device comprising:
a bulk semiconductor substrate;
an isolation region over the bulk semiconductor substrate;
a first sub-fin contacting a first sidewall of the isolation region, wherein the first sub-fin is of p-type, wherein a lower portion of the first sub-fin is doped with carbon, and an upper portion of the first sub-fin is substantially free from carbon;
a second sub-fin contacting a second sidewall of the isolation region, with the first sidewall and the second sidewall being opposing sidewalls of the isolation region, wherein the second sub-fin is of n-type, and wherein an entirety of the second sub-fin is free from carbon;
a first semiconductor fin overlapping the first sub-fin and protruding higher than the isolation region;
a second semiconductor fin overlapping the second sub-fin and protruding higher than the isolation region;
a first gate stack on the first semiconductor fin; and
a second gate stack on the second semiconductor fin.
10. The semiconductor device of claim 9 further comprising:
a p-type well region extending into the first sub-fin and the first semiconductor fin, wherein the p-type well region comprises a first lower portion in the bulk semiconductor substrate and overlapped by a first portion of the isolation region; and
an n-type well region extending into the second sub-fin and the second semiconductor fin, wherein the n-type well region comprises a second lower portion in the bulk semiconductor substrate and overlapped by a second portion of the isolation region.
11. The semiconductor device of claim 10 , wherein the first lower portion of the p-type well region further comprises carbon.
12. The semiconductor device of claim 10 , wherein the second lower portion of the n-type well region further comprises carbon.
13. The semiconductor device of claim 12 , wherein the n-type well region further comprises a third lower portion overlapped by a third portion of the isolation region, wherein the third lower portion is free from carbon.
14. The semiconductor device of claim 12 further comprises a p-type anti-punch-through region in the first sub-fin, wherein the p-type anti-punch-through region is further doped with carbon.
15. The semiconductor device of claim 10 , wherein the p-type well region has a carbon concentration in a range between about 1×10 17 /cm 3 and about 1×10 19 /cm 3 .
16. The semiconductor device of claim 10 , wherein the p-type well region extends to a top surface of the first semiconductor fin.
17. A semiconductor device comprising:
a bulk semiconductor substrate;
an isolation region over the bulk semiconductor substrate;
a sub-fin contacting a sidewall of the isolation region;
a carbon-doped region comprising:
a first portion extending into a lower portion of the sub-fin;
a second portion extending directly underlying a part of the isolation region;
a semiconductor fin overlapping the sub-fin and protruding higher than the isolation region; and
a gate stack on the semiconductor fin.
18. The semiconductor device of claim 17 , wherein the carbon-doped region has a first top surface lower than a second top surface of the isolation region.
19. The semiconductor device of claim 17 , wherein the sub-fin comprises a silicon fin.
20. The semiconductor device of claim 17 , wherein the carbon-doped region has a carbon concentration in a range between about 1×10 17 /cm 3 and about 1×10 19 /cm 3 .