Power semiconductor module
The present invention relates to a power semiconductor module including a first heat dissipation substrate, a semiconductor chip, a lead plate, a PCB, and a heat dissipation plate that are packaged within a casing, wherein dualization of a heat dissipation structure is applied to facilitate superior heat dissipation performance compared to a conventional power semiconductor module.
1. A power semiconductor module comprising:
a first heat dissipation substrate;
a semiconductor chip positioned on the first heat dissipation substrate, and bonded in a form of a flip chip to the first heat dissipation substrate;
a lead plate provided directly on the semiconductor chip;
a thermal interface material layer (TIM layer) positioned on the lead plate;
a printed circuit board (PCB) formed on the TIM layer; and
a second heat dissipation substrate formed on the PCB,
wherein a first copper layer is formed at an upper side of the TIM layer, a second copper layer is formed at a lower side of the TIM layer, and a lower portion of the second heat dissipation substrate is formed penetrating through the PCB and in contact with the first copper layer at an upper side of the TIM layer.
2. The power semiconductor module of claim 1 , wherein
an adhesive layer is provided to attach the lead plate and the PCB.
3. The power semiconductor module of claim 2 , wherein the adhesive layer is composed of nanoparticles each having a diameter of 1 to 50 nm, and has a porous structure.
4. The power semiconductor module of claim 1 , wherein the TIM layer is made of any one selected among alumina, silicon nitride, aluminum nitride, zinc oxide, titanium dioxide, and silica.
5. The power semiconductor module of claim 1 , wherein the TIM layer is formed by dispersing any one selected among alumina, silicon nitride, aluminum nitride, zinc oxide, titanium dioxide, and silica in a form of particles in a polymer.
6. The power semiconductor module of claim 5 , wherein the polymer is any one selected among polytetrafluoroethylene (PTFE), polyethylenceterephthalate (PET), polyethersulfone (PES), polyimide (PI), polycarbonate (PC), polyurethane (PU), polymethylmethacrylate (PMMA), and polyethylenenaphthalate (PEN).
7. The power semiconductor module of claim 1 , wherein the TIM layer is provided with oxidized or plated copper layers formed at opposite surfaces of the TIM layer.
8. The power semiconductor module of claim 1 , wherein the semiconductor chip is bonded using any one or an alloy of two or more selected among copper (Cu), silver (Ag), aluminum (Al), nickel (Ni), tin (Sn), and molybdenum (Mo).
9. The power semiconductor module of claim 1 , wherein the semiconductor chip includes an insulated-gate bipolar transistor (IGBT) and a diode.
10. The power semiconductor module of claim 1 , wherein a casing for making the power semiconductor module airtight is provided, and
the first heat dissipation substrate is formed being in contact with a lower part of an inside surface of the casing, and the second heat dissipation substrate is formed being in contact with an upper part of an inside surface of the casing.
11. The power semiconductor module of claim 1 , wherein a casing for making the power semiconductor module airtight is provided, and
at a lower part of the casing, a part of the first heat dissipation substrate is formed penetrating through the casing and protruding to outside, and at an upper part of the casing, a part of the second heat dissipation substrate is formed penetrating through the casing and protruding to outside.