Field managed group III-V field effect device with epitaxial back-side field plate

1. A semiconductor device having a back-side field plate, the semiconductor device comprising:

a buffer layer comprising a first compound semiconductor material, the buffer layer being epitaxial to a crystalline substrate;

field plate layer disposed on a surface of the buffer layer;

a first channel layer disposed over the field plate layer, the first channel layer comprising the first compound semiconductor material;

a region comprising a two-dimensional electron gas, the two-dimensional electron gas formed at an interface between the first channel layer and a second channel layer, the second channel layer comprising a second compound semiconductor material in physical contact with the first channel layer;

a first back-side field plate that is formed by a region of the field plate layer and is electrically isolated from other regions of the field plate layer; and

a gate, a source contact, and a field plate contact, the field plate contact coupled to the back-side filed plate, the source contact is disposed along a first dimension of the gate, and the field plate contact is disposed along a second dimension of the gate.

2. The semiconductor device according to claim 1 , wherein the field plate layer comprises a deactivated p-type compound semiconductor material and the first back-side field plate comprises an activated p-type compound semiconductor material.

3. The semiconductor device according to claim 1 , wherein the field plate layer comprises an unintentionally doped compound semiconductor material and the first back side filed plate comprises an activated p-type compound semiconductor material that is disposed in trench in the unintentionally doped compound semiconductor material, the trench having an opening in the direction of the two-dimensional electron gas.

4. The semiconductor device according to claim 1 , wherein the first compound semiconductor is gallium nitride and the second compound semiconductor is aluminum gallium nitride.

5. The semiconductor device according to claim 1 , the field plate layer comprises an aluminum nitride material or an aluminum gallium nitride material, and the first backside field plate is formed by a two-dimensional electron gas formed at an interface between the buffer layer and the aluminum nitride material or aluminum gallium nitride material.

6. A method of manufacturing a semiconductor device having a back-side field plate, the method comprising:

forming buffer layer on a substrate, the buffer layer comprising a first compound semiconductor material;

forming a field plate layer on the buffer layer;

forming a first channel layer on the field plate layer, the first channel laver comprising the first compound semiconductor material;

forming a two-dimensional electron gas by forming a second channel layer on the first channel layer, the second channel layer comprising a second compound semiconductor material; and

forming a back-side field plate by patterning the field plate layer; and

forming a gate, a source contact, and a field plate contact, the field plate contact coupled to the back-side filed plate, the source contact is disposed along a first dimension of the gate, and the field plate contact is disposed along a second dimension of the gate.

7. The method of claim 6 , wherein the field plate layer comprises a conductive layer of an n-type material and a field plate barrier layer, and the forming the back-side field plate by patterning the field plate layer comprises:

forming a mask on the second channel layer, the mask determining a geometry of the back-side field plate; and

isolating the back-side field plate from the other regions of the field plate layer by selectively damaging an area of the n-type material exposed by the mask using an ion implantation process.

8. The method of claim 7 , wherein the mask comprises a gate, source, or a drain of the semiconductor device.

9. The method according to aspect 6 , wherein the field plate layer comprises a conductive layer of an n-type material and a field plate barrier layer, and the forming the back-side field plate by patterning the field plate layer comprises:

forming a mask on the field plate barrier layer, the mask determining a geometry of the back-side field plate; and

isolating, before forming the second channel layer, the back-side field plate from other regions of the field plate layer by selectively damaging an area of the n-type material exposed by the mask using an ion implantation process.

10. The method of claim 9 , further comprising:

growing the second channel layer at a lower temperature than an annealing or activation temperature of the n-type material.

11. The method of claim 6 , wherein the field plate layer comprises a region of the buffer layer, and the forming the back-side field plate by patterning the field plate layer comprises:

etching, before forming first channel layer, a trench in the buffer layer;

forming a conductive layer of p-type material in the trench and over a surface of the buffer layer; and

removing the conductive layer of p-type material from the surface of the buffer layer.

12. The method of claim 11 , wherein the removing the conductive layer of p-type material comprises using a chemical mechanical planarization process to etch the p-type material from the surface of the buffer layer.

13. The method of claim 11 , wherein the field plate layer comprises a region of the buffer layer, and the forming the back-side field plate by patterning the field plate layer comprises:

etching, before forming the first channel layer, a trench in the buffer layer;

forming a conductive layer of n-type material in the trench and over a surface of the buffer layer;

forming a protective layer of material on the conductive layer of n-type mated al the trench; and

etching the conductive layer of n-type material from the surface of the buffer layer.

14. The method of claim 6 , wherein the field plate layer comprises a conductive layer of a p-type material, and the forming the back-side field plate by patterning the field plate layer comprises:

deactivating, after forming the second channel layer, the p-type material by using an annealing process to diffuse a deactivating material into the p-type material;

forming a mask comprising a material selected to absorb light that has at least a threshold energy level, the mask covering an area above the p-type material corresponding to a geometry of the back-side field plate; and

selectively activating the area above the p-type material by heating the semiconductor device in the presence of an activating material using a heat source disposed above the mask, the heat source selected to radiate light having at least the threshold energy level.

15. The method of claim 14 , wherein the p-type material is magnesium doped gallium nitride or carbon doped gallium nitride.

16. The method of claim 14 , wherein the deactivating material is ammonia or hydrogen and the activating material is nitrogen.

17. The method of claim 14 , wherein the mask is polysilicon or a refractory metal.

18. The method of claim 6 , wherein the field plate layer comprises a conductive layer of an p-type material, the forming the back-side field plate by patterning the field plate layer comprises:

forming, after forming the second channel layer, a mask covering an area of the second channel layer above the p-type material corresponding to a geometry of the back-side field plate; and

deactivating areas of the p-type material exposed by the mask by using an annealing process to diffuse a deactivating material into the p-type material.

19. The method of claim 18 , wherein the mask is a metal and the deactivating material is hydrogen.

20. The method of claim 18 , herein the mask comprises a material selected to reflect light.

21. The method of claim 11 , where field plate layer comprises a conductive layer of an p-type material, the forming the back-side field plate by patterning the field plate layer comprises:

forming, after forming the second channel layer, a mask covering an area of the second channel layer above the p-type material corresponding to a geometry of the back-side field plate; and

deactivating areas of the p-type material exposed by the mask by implanting a deactivating material into the p-type material.

22. The method of claim 1 , wherein the field plate layer comprises the buffer layer and a field plate barrier layer, and the forming the back-side field plate by patterning the field plate layer comprises:

selectively implanting, after forming the second channel layer and before forming a device contact, an n-type dopant material in an area of the buffer layer corresponding to the back-side field plate; and

selectively activating the area of the buffer layer by annealing the semiconductor device in the presence of an activating material.

23. The method of claim 6 , wherein the field plate layer comprises the buffer layer and a field plate barrier layer, and forming the back-side field plate by patterning the field plate layer comprises:

selectively implanting, before forming first channel layer, an n-type dopant material in a region of the buffer layer corresponding to the back-side field plate; and

selectively activating, before forming the first channel layer, the region implanted with the n-type dopant material.

24. The method of claim 6 , wherein the field plate layer comprises an aluminum nitride material or an aluminum gallium nitride material, and forming the back-side field plate by patterning the field play layer comprises etching or deactivating a region of the field plate layer to form a field plate region, the first backside field plate being formed by a two-dimensional electron gas formed at an interface between the buffer layer and field plate region.

25. A transistor having a backside field plate, the transistor comprising:

a channel layer comprising a first two-dimensional electron gas; and

a back-side field plate disposed between the channel layer and a crystalline substrate, the back-side field plate comprising a second two-dimensional electron gas, the second two-dimensional electron gas disposed over a smaller area than the first two-dimensional electron gas; and

a gate, a source contact, and a field plate contact, the field plate contact coupled to the back-side filed plate, the source contact is disposed along a first dimension of the gate, and the field plate contact is disposed along a second dimension of the gate.

26. The transistor of claim 25 , wherein the second two-dimensional electron gas is formed at an interface between a gallium nitride layer and a patterned layer of aluminum nitride material or aluminum gallium nitride material.

27. The transistor of claim 25 , further comprising:

a buffer layer comprising a first compound semiconductor material, the buffer layer being epitaxial to the crystalline substrate; and

field plate layer disposed on a surface of the buffer layer;

wherein:

the back-side field plate further comprises a field plate region of the field plate layer that is electrically isolated from other regions of the field plate layer;

the channel layer further comprises:

a first channel layer disposed over the field plate layer, the first channel layer comprising the first compound semiconductor material; and

a second channel layer comprising a second compound semiconductor material in physical contact with the first channel layer.

28. The transistor of claim 25 , wherein the field plate layer is epitaxial to the buffer layer.

29. The transistor of claim 25 , wherein the field plate layer comprises a deactivated compound semiconductor material and the field plate region comprises an activated compound semiconductor material.

30. The transistor of claim 25 , wherein the first compound semiconductor is gallium nitride and the second compound semiconductor is aluminum gallium nitride.