Controlling the number of powered vector lanes via a register field
The vector data path is divided into smaller vector lanes. A register such as a memory mapped control register stores a vector lane number (VLX) indicating the number of vector lanes to be powered. A decoder converts this VLX into a vector lane control word, each bit controlling the ON of OFF state of the corresponding vector lane. This number of contiguous least significant vector lanes are powered. In the preferred embodiment the stored data VLX indicates that 2 VLX contiguous least significant vector lanes are to be powered. Thus the number of vector lanes powered is limited to an integral power of 2. This manner of coding produces a very compact controlling bit field while obtaining substantially all the power saving advantage of individually controlling the power of all vector lanes.
1. An apparatus comprising:
a register configured to store a vector lane data;
a vector data path having a plurality of vector lanes, wherein each of the plurality of vector lanes is configured to be separately and selectively powered on;
a decoder coupled to the register and to the vector data path, wherein: the decoder is configured to receive the vector lane data from the register and to output a vector lane control word, wherein the vector lane control word is configured to specify a number of the plurality of vector lanes to power on as a power of two; and
control logic configured to control the powering on of each of the plurality of vector lanes in response to the vector lane control word.
2. The apparatus of claim 1 , wherein:
the decoder determines a number of vector lanes of the plurality of vector lanes based on the vector lane data.
3. The apparatus of claim 2 , wherein:
the number of vector lanes is not an integer power of two and a next higher integer power of two number of vector lanes is powered on.
4. The apparatus of claim 1 , wherein:
the number of the plurality of vector lanes powered on are a set of contiguous least significant vector lanes.
5. The apparatus of claim 1 , wherein:
the vector lane data includes an instruction field.
6. The apparatus of claim 1 , wherein:
the plurality of vector lanes are configured from least significant vector lanes to most significant vector lanes; and
the plurality of vector lanes are configured to be powered on from the least significant vector lanes toward the most significant vector lanes.
7. The apparatus of claim 1 , wherein:
the vector lane data includes a number of bits.
8. The apparatus of claim 7 , wherein:
the number of bits of the vector lane data is less than the number of the plurality of vector lanes of the vector data path.
9. The apparatus of claim 7 , wherein:
each bit of the vector lane control word corresponds to a respective one of the plurality of vector lanes.
10. A method comprising:
storing vector lane data in a register;
reading the register and extracting the vector lane data from the register;
determining a vector lane control word based on the vector lane data, wherein the vector lane control word is configured to specify a number of a plurality of vector lanes to power on as a power of two; and
powering on the number of the plurality of the vector lanes in response to the vector lane control word.
11. The method of claim 10 , wherein:
each of the plurality of vector lanes is configured to be separately and selectively powered on.
12. The method of claim 10 , further comprising:
powering off unused vector lanes of the plurality of vector lanes in response to the vector lane control word.
13. The method of claim 12 , wherein:
the plurality of vector lanes are configured from least significant vector lanes to most significant vector lanes.
14. The method of claim 13 , wherein:
the unused vector lanes include a portion of the most significant vector lanes.
15. The method of claim 10 , further comprising:
extracting an instruction field from the register.
16. The method of claim 10 , wherein:
the vector lane control word includes a number of bits having a bit state controlling a corresponding vector lane of the plurality of vector lanes to be powered on.
17. The method of claim 10 , wherein:
the vector lane control word includes a number of bits having a bit state controlling the vector lane of the plurality of vector lanes to be powered on corresponding to contiguous least significant vector lanes.
18. The method of claim 10 , wherein:
the step of determining the vector lane control word includes reading a look-up table having a plurality of entries consisting of vector lane control words indexed by a vector lane number field.
19. The method of claim 10 , wherein:
the vector lane data includes a default value configured to power on a single vector lane.
20. The method of claim 10 , wherein:
the vector lane data includes a default value configured to power on all the vector lanes.