IP Library Granted Patent US 11,361,807
Granted Patent B2
US 11,361,807 · App. 16/972,693 · Granted Jun 14, 2022

Semiconductor device

Inventors: Shunpei Yamazaki (Setagaya, JP); Hajime Kimura (Atsugi, JP); Atsushi Miyaguchi (Hadano, JP); Yoshiaki Oikawa (Atsugi, JP)
Assignee: Semiconductor Energy Laboratory Co., Ltd.
G11C11/405G06N3/04G06N3/063G06N3/08H01L27/108H01L29/7869
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Quick Facts
Patent No.
US 11,361,807
App. No.
16/972,693
Granted
Jun 14, 2022
Kind
B2
Abstract

A semiconductor device that enables lower power consumption and data storage imitating a human brain is provided. The semiconductor device includes a control unit, a memory unit, and a sensor unit. The memory unit includes a memory circuit and a switching circuit. The memory circuit includes a first transistor and a capacitor. The switching circuit includes a second transistor and a third transistor. The first transistor and the second transistor include a semiconductor layer including a channel formation region with an oxide semiconductor, and a back gate electrode. The control unit has a function of switching a signal supplied to the back gate electrode, in accordance with a signal obtained at the sensor unit.

Claims (46)

1. A semiconductor device comprising a control unit, a memory unit, and a sensor unit,

wherein the memory unit comprises a first memory circuit part, a second memory circuit part, and a switching circuit,

wherein the first memory circuit part comprises a plurality of first memory circuits,

wherein the second memory circuit part comprises a plurality of second memory circuits,

wherein the switching circuit is configured to control amount of current flowing between the first memory circuit part and the second memory circuit part,

wherein each of the plurality of first memory circuits comprises a first transistor and a first capacitor,

wherein the switching circuit comprises a second transistor and a third transistor,

wherein the first transistor and the second transistor comprise a semiconductor layer comprising a channel formation region with an oxide semiconductor, a gate electrode, and a back gate electrode, and

wherein the control unit is configured to switch signals supplied to the back gate electrode of the first transistor and the back gate electrode of the second transistor, in accordance with a signal obtained at the sensor unit.

2. The semiconductor device according to claim 1 ,

wherein each of the plurality of second memory circuits comprises a fourth transistor and a second capacitor, and

wherein the control unit is electrically connected to a back gate electrode of the fourth transistor.

3. The semiconductor device according to claim 1 , wherein the switching circuit is a programmable device being able to store configuration data.

4. The semiconductor device according to claim 1 , wherein the switching circuit is provided between wirings between one of the plurality of first memory circuits and one of the plurality of second memory circuits.

5. The semiconductor device according to claim 1 , wherein the third transistor is a p-channel transistor.

6. The semiconductor device according to claim 1 , wherein the sensor unit comprises at least one of a brain wave sensor, a pulse wave sensor, a blood pressure sensor, and a temperature sensor.

7. A semiconductor device comprising a control unit, a memory unit, and a sensor unit,

wherein the memory unit comprises a first memory circuit part, a second memory circuit part, and a switching circuit,

wherein the first memory circuit part comprises a plurality of first memory circuits,

wherein the second memory circuit part comprises a plurality of second memory circuits,

wherein the switching circuit is configured to control amount of current flowing between the first memory circuit part and the second memory circuit part,

wherein each of the plurality of first memory circuits comprises a first transistor and a first capacitor,

wherein the switching circuit comprises a second transistor and a third transistor,

wherein each of the plurality of second memory circuits comprises a fourth transistor and a second capacitor,

wherein each of the first transistor, the second transistor, and the fourth transistor comprises a semiconductor layer comprising a channel formation region with an oxide semiconductor, a gate electrode, and a back gate electrode, and

wherein the control unit is configured to switch signals supplied to the back gate electrode of the first transistor, the back gate electrode of the second transistor, and the back gate electrode of the fourth transistor, in accordance with a signal obtained at the sensor unit.

8. The semiconductor device according to claim 7 , wherein the switching circuit is a programmable device being able to store configuration data.

9. The semiconductor device according to claim 7 , wherein the switching circuit is provided between wirings between one of the plurality of first memory circuits and one of the plurality of second memory circuits.

10. The semiconductor device according to claim 7 , wherein the third transistor is a p-channel transistor.

11. The semiconductor device according to claim 7 , wherein the sensor unit comprises at least one of a brain wave sensor, a pulse wave sensor, a blood pressure sensor, and a temperature sensor.

12. A semiconductor device comprising a control unit, a memory unit, and a sensor unit,

wherein the memory unit comprises a first memory circuit part, a second memory circuit part, and a switching circuit,

wherein the first memory circuit part comprises a plurality of first memory circuits,

wherein the second memory circuit part comprises a plurality of second memory circuits,

wherein the switching circuit is configured to control amount of current flowing between the plurality of first memory circuits and the plurality of second memory circuits,

wherein each of the plurality of first memory circuits comprises a first transistor and a first capacitor,

wherein one of a source and a drain of the first transistor is electrically connected to one electrode of the first capacitor,

wherein the switching circuit comprises a second transistor and a third transistor,

wherein each of the plurality of second memory circuits comprises a fourth transistor and a second capacitor,

wherein one of a source and a drain of the second transistor is electrically connected to a gate electrode of the third transistor,

wherein each of the first transistor, the second transistor, and the fourth transistor comprises a semiconductor layer comprising a channel formation region with an oxide semiconductor, a gate electrode, and a back gate electrode, and

wherein the control unit is configured to switch signals supplied to the back gate electrode of the first transistor, the back gate electrode of the second transistor, and the back gate electrode of the fourth transistor, in accordance with a signal obtained at the sensor unit.

13. The semiconductor device according to claim 12 , wherein the switching circuit is a programmable device being able to store configuration data.

14. The semiconductor device according to claim 12 , wherein the switching circuit is provided between wirings between one of the plurality of first memory circuits and one of the plurality of second memory circuits.

15. The semiconductor device according to claim 12 , wherein the third transistor is a p-channel transistor.

16. The semiconductor device according to claim 12 , wherein the sensor unit comprises at least one of a brain wave sensor, a pulse wave sensor, a blood pressure sensor, and a temperature sensor.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 7, 2020
From: YAMAZAKI, SHUNPEI; KIMURA, HAJIME; MIYAGUCHI, ATSUSHI; OIKAWA, YOSHIAKI
To: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Reel/Frame 054565/0507 →
Priority Claims (2)
JP JP2018-114810 · Jun 15, 2018 · national
JP JP2018-114813 · Jun 15, 2018 · national
Continuity (1)
Related Publication 20210257015A1 · Aug 19, 2021
Cited By (1)
US 12,211,539