Semiconductor memory device and method of operating the semiconductor memory device

1. A semiconductor memory device comprising:

a memory cell array including a plurality of memory blocks, which are assigned as a plurality of normal blocks, a plurality of first replacement blocks, a plurality of second replacement blocks, a first content addressable memory (CAM) block, and a second CAM block;

a peripheral circuit configured to perform an erase operation and a program operation on the plurality of memory blocks; and

control logic configured to control the peripheral circuit to perform a growing bad block check operation on a target block during the program operation on a selected target block among the normal memory blocks,

wherein the control logic controls the peripheral circuit to perform the erase operation on the target block before performing the program operation on the target block, and perform the growing bad block check operation immediately before the erase operation or perform the growing bad block check operation immediately after performing the erase operation.

2. The semiconductor memory device of claim 1 , wherein the peripheral circuit checks threshold voltages of select transistors included in the target block during the growing bad block check operation, and counts the number of select transistors of which the threshold voltage is out of a normal range among the select transistors.

3. The semiconductor memory device of claim 2 , wherein when the number of the select transistors of which the threshold voltages are out of the normal range is greater than a threshold count, the control logic determines the target block as a growing bad block, and selects a replacement block for replacing the target block from among the plurality of second replacement blocks.

4. The semiconductor memory device of claim 3 , wherein the control logic controls the peripheral circuit to perform the program operation on the selected replacement block.

5. The semiconductor memory device of claim 4 , wherein the control logic controls the peripheral circuit to update information on the target block and the selected replacement block in the second CAM block after the program operation on the selected replacement block is completed.

6. The semiconductor memory device of claim 1 , wherein the first replacement blocks are memory blocks for replacing memory blocks determined as initial bad blocks among the normal blocks.

7. The semiconductor memory device of claim 6 , wherein each of the initial bad blocks is a bad memory block detected during a test process after manufacturing of the semiconductor memory device is completed.

8. The semiconductor memory device of claim 6 , wherein the first CAM block stores system data including option parameter information and information on operation voltages and information on the initial bad blocks.

9. The semiconductor memory device of claim 1 , further comprising:

a word line test circuit configured to detect a defect of local lines connected to the target blocks during the growing bad block check operation.

10. A semiconductor memory device comprising:

a memory cell array including a plurality of normal blocks, a plurality of replacement blocks, and a CAM block;

a peripheral circuit configured to perform an erase operation and a program operation on the plurality of memory blocks;

a word line test circuit coupled to the plurality of memory blocks through local lines and configured to detect a defect in a memory block from the plurality of memory blocks through the local lines; and

control logic configured to control the peripheral circuit to perform a growing bad block check operation on the target block during the program operation on a selected target block among the normal memory blocks,

wherein the control logic controls the peripheral circuit to perform the program operation on a selected replacement block among the plurality of replacement blocks instead of the target block according to a result of the growing bad block check operation,

wherein the control logic controls the peripheral circuit to perform the erase operation on the target block during the program operation on the target block, and perform the growing bad block check operation before the erase operation or perform the growing bad block check operation after performing the erase operation.

11. The semiconductor memory device of claim 10 , wherein the peripheral circuit checks threshold voltages of select transistors included in the target block during the growing bad block check operation, and counts the number of select transistors of which the threshold voltages are out of a normal range among the select transistors.

12. The semiconductor memory device of claim 10 , wherein the word line test circuit applies a test voltage to the local lines during the growing bad block check operation, and compares a measured voltage and a reference voltage of the local lines to detect the defect of the target block.

13. A method of operating a semiconductor memory device comprising:

receiving a command corresponding to a program operation on a target block;

performing a growing bad block check operation on the target block before an erase operation;

performing the erase operation on the target block immediately after the growing bad block check operation in response to the command; and

selecting a replacement block for replacing the target block and performing the program operation when the target block is determined as a growing bad block as a result of the growing bad block check operation.

14. The method of claim 13 , further comprising:

storing information on the target block and information on the replacement block in a CAM block after the program operation on the replacement block is completed.

15. The method of claim 13 , wherein the growing bad block check operation compares the number of select transistors out of a normal threshold voltage range among select transistors included in the target block.

16. The method of claim 13 , wherein the growing bad block check operation applies a test voltage to local lines of the target block and compares a measured voltage and a reference voltage of the local lines.