Multiple nano layer transistor layers with different transistor architectures for improved circuit layout and performance
A semiconductor device includes a plurality of nano-channel field-effect transistor stacks positioned adjacent to each other such that source-drain regions are shared between adjacent nano-channel field-effect transistor stacks, each nano-channel field-effect transistor stack including at least two nano-channel field-effect transistors and corresponding source/drain regions vertically separated from each other.
1. A semiconductor device comprising:
a first FET (field-effect transistor) device formed on a lower level of a substrate, the first FET device including at least one first nano-channel that connects source/drain regions of the first FET device;
a second FET device formed on an upper level of the substrate and positioned directly above the first FET device with a spacer separating the first FET device from the second FET device, the second FET device including at least one second nano-channel that connects source/drain regions of the second FET device;
a third FET device formed on the lower level of the substrate adjacent to the first FET device, the third FET device including at least one third nano-channel that connects source/drain regions of the third FET device, wherein a lower level epitaxially grown region provides one source/drain region of the third FET device which is shared with one source/drain region of the first FET device;
a fourth FET device formed on the upper level of the substrate adjacent to the second FET device and positioned directly above the third FET device with a spacer separating the third FET device from the fourth FET device, the fourth FET device including at least one fourth nano-channel that connects source/drain regions of the fourth FET device, wherein an upper epitaxially grown region provides one source/drain region of the fourth FET device which is shared with one source/drain region of the second FET device.
2. The semiconductor device of claim 1 , wherein the semiconductor device is doped so that the first FET forms a p-channel FET and the third FET forms a tunneling FET.
3. The semiconductor device of claim 1 , wherein the semiconductor device is doped so that the second FET forms a p-channel FET and the fourth FET forms a tunneling FET.
4. The semiconductor device of claim 1 , wherein the semiconductor device is doped so that the first FET forms an n-channel FET and the third FET forms a tunneling FET.
5. The semiconductor device of claim 1 , wherein the semiconductor device is doped so that the second FET forms an n-channel FET and the fourth FET forms a tunneling FET.
6. The semiconductor device of claim 1 , wherein the semiconductor device is doped so that the first FET forms a tunneling FET and the third FET forms a tunneling FET.
7. The semiconductor device of claim 1 , wherein the semiconductor device is doped so that the second FET forms a tunneling FET and the fourth FET forms a tunneling FET.
8. The semiconductor device of claim 1 , wherein the first and second FETs provide
a first nano-channel FET stack, and the third and fourth FETs provide a second nano-channel FET stack, the device further comprising
a fifth FET device formed on the lower level of the substrate adjacent to the third FET device, the fifth FET device including at least one fifth nano-channel that connects source/drain regions of the fifth FET device, wherein a another lower level epitaxially grown region provides one source/drain region of the fifth FET device which is shared with one source/drain region of the third FET device; and
a sixth FET device formed on the upper level of the substrate adjacent to the fourth FET device and positioned directly above the fifth FET device with a spacer separating the fifth FET device from the sixth FET device, the sixth FET device including at least one sixth nano-channel that connects source/drain regions of the sixth FET device, wherein another upper epitaxially grown region provides one source/drain region of the sixth FET device which is shared with one source/drain region of the fourth FET device, wherein the fifth and sixth FETs provide a third nano-channel FET stack, wherein each given source/drain region is selectively doped with either p-type dopant or n-type dopant to result in different combinations of adjacent nano-channel FET stacks, the different combinations including n-channel FETs (NFETs) positioned adjacent to p-channel FETs (PFETs) resulting in tunneling field-effect transistors (TFETs) formed therebetween.
9. The semiconductor device of claim 8 , wherein
the semiconductor device is doped so that the first FET forms a PFET, the third FET forms a TFET, and the fifth FET forms an NFET.
10. The semiconductor device of claim 8 , wherein
the p-type dopant is boron and the n-type dopant is phosphorus or arsenic.
11. The semiconductor device of claim 1 , wherein:
the first FET device, the first FET device being doped to form a first tunneling FET;
the second FET device being doped to form a second tunneling FET;
the third FET device being doped to form a third tunneling FET; and
the fourth FET device being doped to form a fourth tunneling FET.