Integrated power amplifier

1. A semiconductor structure comprising:

a semiconductor-on-insulator (SOI) substrate;

a silicon-based transistor that includes a portion of a silicon layer of the SOI substrate;

a group III nitride transistor device that is embedded in the SOI substrate and is adjacent to the silicon-based transistor;

a first electrical contact of a first level of interconnect wires that connects a first source/drain structure of the silicon-based transistor to a gate structure of the group III nitride transistor device; and

a second electrical contact of a second level of interconnect wires that connects a second device pad to the second level of interconnect wires;

wherein:

current flow through the group III nitride transistor device from a first device pad to the second device pad is controlled by gate current supplied from the first electrical contact connected to the first source/drain structure of the silicon-based transistor;

the semiconductor-on-insulator (SOI) substrate includes, from bottom to top, a (111) silicon layer, a buried insulator layer, and a (100) silicon layer;

the group III nitride transistor device includes at least one Group III nitride material layer embedded within a trench that extends through the (100) silicon layer and the buried insulator layer and into an upper portion of the (111) silicon layer, making contact directly with the (111) silicon layer; and

the group III nitride transistor device is included in a trench in the SOI substrate.

2. The semiconductor structure of claim 1 , wherein the group III nitride transistor device is a Monolithic Microwave Integrated Circuit (MMIC).

3. The semiconductor structure of claim 1 , wherein at least one Group III nitride material, of the group III nitride transistor device, abuts a sub-surface of a (111) silicon layer of the SOI substrate.

4. The semiconductor structure of claim 1 , wherein at least one Group III nitride material, of the group III nitride transistor device, has a topmost surface that is above, coplanar with, or below a top surface of a (100) silicon layer of the SOI substrate.

5. The semiconductor structure of claim 1 , wherein the group III nitride transistor device comprises (i) a Group III nitride buffer layer and (ii) a Group III nitride channel layer located on the Group III nitride buffer layer, wherein the Group III nitride channel layer has a top surface that is above a top surface of a (100) silicon layer of the SOI substrate.

6. The semiconductor structure of claim 1 , wherein the group III nitride transistor device comprises (i) a buffer layer comprising GaN and (ii) a channel layer comprising AlGaN.

7. The semiconductor structure of claim 1 , wherein the spacer structure is in direct contact with entire sidewalls of the at least one Group III nitride material layer.

8. The semiconductor structure of claim 1 , wherein:

the second electrical contact connects the second device pad of the group III nitride transistor device to an induction coil.

9. The semiconductor structure of claim 1 , wherein:

the trench includes a spacer structure located between sidewalls of the trench and sidewalls of the at least one Group III nitride layer of the group III nitride transistor device; and

the spacer structure comprises a first sidewall spacer adjoined to the sidewalls of the trench and a second sidewall spacer adjoined to the sidewalls of the at least one Group III nitride layer.

10. The semiconductor structure of claim 9 , wherein the first sidewall spacer comprises silicon nitride, and wherein the second sidewall spacer comprises silicon dioxide, aluminum oxide or hafnium oxide.

11. A method of forming a semiconductor structure comprising:

forming a semiconductor-on-insulator (SOI) substrate;

forming a silicon-based transistor that includes a portion of a silicon layer of the SOI substrate;

forming a group III nitride transistor device that is embedded in the SOI substrate and is adjacent to the silicon-based transistor;

a first electrical contact of a first level of interconnect wires that connects a first source/drain structure of the silicon-based transistor to a gate structure of the group III nitride transistor device; and

a second electrical contact of a second level of interconnect wires that connects a second device pad to the second level of interconnect wires;

wherein:

current flow through the group III nitride transistor device from a first device pad to the second device pad is controlled by gate current supplied from the first electrical contact connected to the first source/drain structure of the silicon-based transistor;

the semiconductor-on-insulator (SOI) substrate includes, from bottom to top, a (111) silicon layer, a buried insulator layer, and a (100) silicon layer;

the group III nitride transistor device includes at least one Group III nitride material layer embedded within a trench that extends through the (100) silicon layer and the buried insulator layer and into an upper portion of the (111) silicon layer, making contact directly with the (111) silicon layer; and

the group III nitride transistor device is included in a trench in the SOI substrate.

12. The method of claim 11 , wherein the group III nitride transistor device is a Monolithic Microwave Integrated Circuit (MMIC).

13. The method of claim 11 , wherein:

the trench includes a spacer structure located between sidewalls of the trench and sidewalls of the at least one Group III nitride layer of the group III nitride transistor device; and

the spacer structure comprises a first sidewall spacer adjoined to the sidewalls of the trench and a second sidewall spacer adjoined to the sidewalls of the at least one Group III nitride layer.

14. The method of claim 11 , wherein the group III nitride transistor device comprises (i) a Group III nitride buffer layer and (ii) a Group III nitride channel layer located on the Group III nitride buffer layer, wherein the Group III nitride channel layer has a top surface that is above a top surface of a (100) silicon layer of the SOI substrate.