Capacitor and manufacturing method therefor
A capacitor includes: a semiconductor substrate including at least one substrate trench group; at least one laminated structure, each laminated structure includes n conductive layers and m dielectric layers, the first conductive layer in the n conductive layers is disposed above the semiconductor substrate and in the substrate trench group, the i-th conductive layer in the n conductive layers is provided with the i-th conductive layer trench group, and the (i+1)th conductive layer in the n conductive layers is disposed above the i-th conductive layer and in the i-th conductive layer trench group, where m, n, and i are positive integers, and n≥2, 1≤i≤n−1; a first external electrode connected to some conductive layers; and a second external electrode connected to other conductive layers.
1. A capacitor, comprising:
a semiconductor substrate comprising at least one substrate trench group, the substrate trench group entering the semiconductor substrate downward from an upper surface of the semiconductor substrate;
at least one laminated structure, each laminated structure comprising n conductive layers and m dielectric layer(s), wherein the first conductive layer in the n conductive layers is disposed above the semiconductor substrate and in the substrate trench group, the i-th conductive layer in the n conductive layers is provided with the i-th conductive layer trench group, the (i+1)th conductive layer in the n conductive layers is disposed above the i-th conductive layer and in the i-th conductive layer trench group, and the n conductive layers and the m dielectric layer(s) form a structure that a conductive layer and a dielectric layer are adjacent to each other, where m, n, and i are positive integers, and n≥2, 1≤i≤n−1;
at least one first external electrode, wherein the first external electrode is electrically connected to some conductive layer(s) in the n conductive layers; and
at least one second external electrode, wherein the second external electrode is electrically connected to other conductive layer(s) in the n conductive layers, and a conductive layer in the laminated structure adjacent to each conductive layer in the some conductive layer(s) comprises at least one conductive layer in the other conductive layer(s);
wherein the each laminated structure comprises the first conductive layer of the n conductive layers, a second conductive layer of the n conductive layers, a first dielectric layer of the m dielectric layers, and a second dielectric layer of the m dielectric layers, wherein
the first dielectric layer is disposed between the semiconductor substrate and the first conductive layer, and the second dielectric layer is disposed between the first conductive layer and the second conductive layer; and
the first conductive layer comprises a film layer portion and a trench portion, the first conductive layer is provided with a first conductive layer trench group, and the first conductive layer trench group is disposed in the film layer portion of the first conductive layer and does not enter the trench portion of the first conductive layer, and the second conductive layer is disposed above the first conductive layer and in the first conductive layer trench group; and
the trench portion of the first conductive layer is disposed in the substrate trench group and the substrate trench group is completely filled by the trench portion, the film layer portion of the first conductive layer is disposed above the semiconductor substrate and the first conductive layer trench group in the film layer portion is disposed above the semiconductor substrate.
2. The capacitor according to claim 1 , wherein the i-th conductive layer comprises an i-th film layer portion and an i-th trench portion, and the i-th conductive layer trench group is disposed in the i-th film layer portion of the i-th conductive layer and does not enter the trench portion of the i-th conductive layer.
3. The capacitor according to claim 2 , wherein a thickness of the film layer portion of the first conductive layer ranges from 10 nm to 20 μm.
4. The capacitor according to claim 2 , wherein numbers and/or sizes of conductive layer trenches comprised in different conductive layers in the n conductive layers are the same or different.
5. The capacitor according to claim 2 , wherein a plurality of substrate trenches comprised in the substrate trench group are distributed in an array, and/or a plurality of conductive layer trenches comprised in the i-th conductive layer trench group are distributed in an array.
6. The capacitor according to claim 2 , wherein sizes of a plurality of substrate trenches comprised in the substrate trench group are smaller than a first threshold, and/or sizes of a plurality of conductive layer trenches comprised in the i-th conductive layer trench group are smaller than a second threshold, wherein the first threshold is equal to the second threshold.
7. The capacitor according to claim 1 , wherein the each laminated structure further comprises a third conductive layer of the n conductive layers, and a third dielectric layer of the m dielectric layers, wherein
the third dielectric layer is disposed between the second conductive layer and the third conductive layer;
the second conductive layer comprises a second film layer portion and a second trench portion, the second conductive layer is provided with a second conductive layer trench group, and the second conductive layer trench group is disposed in the second film layer portion of the second conductive layer and does not enter the second trench portion of the second conductive layer, and the third conductive layer is disposed above the second conductive layer and in the second conductive layer trench group;
the second trench portion of the second conductive layer is disposed in the first conductive layer trench group and the first conductive layer trench group is completely filled by the second trench portion of the second conductive layer, the second film layer portion of the second conductive layer is disposed above the film layer portion of the first conductive layer and the second conductive layer trench group in the second film layer portion of the second conductive layer is disposed above the film layer portion of the first conductive layer; and
numbers and sizes of substrate trenches in the substrate trench group are the same as numbers and sizes of second conductive layer trenches in the second conductive layer trench group.
8. The capacitor according to claim 1 , wherein the laminated structure is provided with a step structure, and the step structure is provided with an etching stop layer formed of an insulating material, or an edge of the step structure is provided with a spacer formed of an insulating material.
9. The capacitor according to claim 1 , wherein the semiconductor substrate is formed of a material with a resistivity less than a threshold, or a surface of the semiconductor substrate is provided with a heavily doped conductive layer or conductive region with a resistivity less than a threshold; and
a conductive layer in the laminated structure that is closest to the semiconductor substrate is electrically connected to the first external electrode, and the semiconductor substrate is electrically connected to the second external electrode; or
a conductive layer in the laminated structure that is closest to the semiconductor substrate is electrically connected to the second external electrode, and the semiconductor substrate is electrically connected to the first external electrode.
10. The capacitor according to claim 1 , wherein the capacitor further comprises: an electrode layer disposed above the laminated structure, wherein the electrode layer comprises at least one first conductive region and at least one second conductive region that are separated from each other, the first conductive region forms the first external electrode, and the second conductive region forms the second external electrode;
the first external electrode and/or the second external electrode is electrically connected to a conductive layer in the n conductive layers through an interconnection structure, the interconnection structure comprises at least one insulating layer and a conductive via structure, and the conductive via structure penetrates through the at least one insulating layer to be electrically connected to a conductive layer in the n conductive layers.
11. The capacitor according to claim 1 , wherein the first external electrode is electrically connected to all odd-numbered conductive layers in the n conductive layers, and the second external electrode is electrically connected to all even-numbered conductive layers in the n conductive layers, different laminated structures of the at least one laminated structure share the same first external electrode, and different laminated structures of the at least one laminated structure share the same second external electrode.
12. The capacitor according to claim 1 , wherein the conductive layer comprises at least one of:
a heavily doped polysilicon layer, a metal silicide layer, a carbon layer, a conductive polymer layer, an aluminum layer, a copper layer, a tungsten layer, a titanium layer, a tantalum layer, a platinum layer, a nickel layer, a ruthenium layer, an iridium layer, a rhodium layer, a tantalum nitride layer, a titanium nitride layer, a titanium aluminum nitride layer, a tantalum silicon nitride layer, or a tantalum carbon nitride layer; and
the dielectric layer comprises at least one of:
a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, a metal oxide layer, a metal nitride layer, or a metal oxynitride layer.
13. A method for manufacturing a capacitor, comprising:
producing at least one substrate trench group on a semiconductor substrate, the substrate trench group entering the semiconductor substrate downward from an upper surface of the semiconductor substrate;
producing at least one laminated structure, each laminated structure comprising n conductive layers and m dielectric layers, wherein the first conductive layer in the n conductive layers is disposed above the semiconductor substrate and in the substrate trench group, the i-th conductive layer in the n conductive layers is provided with the i-th conductive layer trench group, the (i+1)th conductive layer in the n conductive layers is disposed above the i-th conductive layer and in the i-th conductive layer trench group, and the n conductive layers and the m dielectric layers form a structure that a conductive layer and a dielectric layer are adjacent to each other, where m, n, and i are positive integers, and n≥2, 1≤i≤n−1; and
producing at least one first external electrode and at least one second external electrode, wherein the first external electrode is electrically connected to some conductive layers in the n conductive layers, and the second external electrode is electrically connected to other conductive layers in the n conductive layers, and a conductive layer in the laminated structure adjacent to each conductive layer in the some conductive layers comprises at least one conductive layer in the other conductive layers;
wherein the each laminated structure comprises the first conductive layer of the n conductive layers, a second conductive layer of the n conductive layers, a first dielectric layer of the m dielectric layers, and a second dielectric layer of the m dielectric layers, wherein
the first dielectric layer is disposed between the semiconductor substrate and the first conductive layer, and the second dielectric layer is disposed between the first conductive layer and the second conductive layer; and
the first conductive layer comprises a film layer portion and a trench portion, the first conductive layer is provided with a first conductive layer trench group, and the first conductive layer trench group is disposed in the film layer portion of the first conductive layer and does not enter the trench portion of the first conductive layer, and the second conductive layer is disposed above the first conductive layer and in the first conductive layer trench group; and
the trench portion of the first conductive layer is disposed in the substrate trench group and the substrate trench group is completely filled by the trench portion, the film layer portion of the first conductive layer is disposed above the semiconductor substrate and the first conductive layer trench group in the film layer portion is disposed above the semiconductor substrate.
14. The capacitor according to claim 1 , wherein numbers and sizes of substrate trenches in the substrate trench group are the same as numbers and sizes of first conductive layer trenches in the first conductive layer trench group.
15. The capacitor according to claim 8 , wherein a plurality of the first conductive layer trench groups is disposed horizontally in the film layer portion of the first conductive layer, an insulating trench is disposed between adjacent first conductive layer trench groups to from the step structure of the laminated structure;
wherein an etching stop layer formed of an insulating material is disposed on surface of the insulating trench, or a spacer formed of an insulating material is disposed on sidewall of the insulating trench.
16. The method for manufacturing a capacitor according to claim 13 , wherein numbers and sizes of substrate trenches in the substrate trench group are the same as numbers and sizes of first conductive layer trenches in the first conductive layer trench group.
17. The method for manufacturing a capacitor according to claim 13 , wherein the each laminated structure further comprises a third conductive layer of the n conductive layers and a third dielectric layer of the m dielectric layers, wherein
the third dielectric layer is disposed between the second conductive layer and the third conductive layer;
the second conductive layer comprises a second film layer portion and a second trench portion, the second conductive layer is provided with a second conductive layer trench group, and the second conductive layer trench group is disposed in the second film layer portion of the second conductive layer and does not enter the second trench portion of the second conductive layer, and the third conductive layer is disposed above the second conductive layer and in the second conductive layer trench group;
the second trench portion of the second conductive layer is disposed in the first conductive layer trench group and the first conductive layer trench group is completely filled by the second trench portion of the second conductive layer, the second film layer portion of the second conductive layer is disposed above the film layer portion of the first conductive layer and the second conductive layer trench group in the second film layer portion of the second conductive layer is disposed above the film layer portion of the first conductive layer; and
numbers and sizes of substrate trenches in the substrate trench group are the same as numbers and sizes of second conductive layer trenches in the second conductive layer trench group.
18. The method for manufacturing a capacitor according to claim 13 , wherein a plurality of the first conductive layer trench groups is disposed horizontally in the film layer portion of the first conductive layer, an insulating trench is disposed between adjacent first conductive layer trench groups to from a step structure of the laminated structure;
wherein an etching stop layer formed of an insulating material is disposed on surface of the insulating trench, or a spacer formed of an insulating material is disposed on sidewall of the insulating trench.