Contact interface engineering for reducing contact resistance

1. A structure comprising:

a transistor comprising a first source/drain region;

a source/drain contact plug over and electrically coupling to the first source/drain region; and

a via over and contacting the source/drain contact plug, the via comprising:

a bottom portion having a first length; and

an upper portion having a second length, wherein the first length is greater than the second length, and both of the first length and the second length are measured in a first direction parallel to a top surface of the source/drain contact plug.

2. The structure of claim 1 , wherein the transistor further comprises:

a gate stack; and

a second source/drain region, wherein the first source/drain region and the second source/drain region are on opposite sides of the gate stack, and the first direction is perpendicular to a direction pointing from the first source/drain region to the second source/drain region.

3. The structure of claim 1 , wherein the bottom portion has a first width, and the upper portion has a second width smaller than the first width, and both of the first width and the second width are measured in a second direction perpendicular to the first direction.

4. The structure of claim 1 , wherein the bottom portion has a first width, and the upper portion has a second width substantially equal to the first width, and both of the first width and the second width are measured in a second direction perpendicular to the first direction.

5. The structure of claim 1 further comprising:

an etch stop layer, wherein the bottom portion of the via is in the etch stop layer; and

a dielectric layer over the etch stop layer, wherein the upper portion of the via is in the dielectric layer.

6. The structure of claim 1 , wherein the via further comprises a top portion laterally extending beyond the upper portion, and wherein there is an abrupt change in lengths of the via from the upper portion to the top portion.

7. The structure of claim 6 further comprising:

an etch stop layer, wherein the bottom portion is in the etch stop layer;

a first dielectric layer over the etch stop layer, wherein the upper portion is in the first dielectric layer; and

a second dielectric layer over the first dielectric layer, wherein the top portion is in the second dielectric layer.

8. The structure of claim 1 , wherein the upper portion has a substantially straight and vertical sidewall, and the bottom portion laterally extends beyond the substantially straight and vertical sidewall.

9. A structure comprising:

a first conductive feature, wherein in a plane view, the first conductive feature has a first length in a first direction, and a first width in a second direction perpendicular to the first direction, and the first width is smaller than the first length; and

a conductive via over and contacting the first conductive feature, wherein the conductive via comprises:

a bottom portion, wherein the bottom portion is elongated with a second length measured in the first direction, and a second width measured in the second direction, with the second width smaller than the second length; and

an upper portion over and joined to the bottom portion, wherein the upper portion has a third length measured in the first direction, and a third width measured in the second direction, with the third length being substantially equal to the third width.

10. The structure of claim 9 , wherein the bottom portion and the upper portion of the conductive via comprise a same homogenous material.

11. The structure of claim 9 , wherein the upper portion has straight sidewalls.

12. The structure of claim 9 , wherein the second length is greater than the third length by a difference, and a ratio of the difference to the first length is in a range between about 0.2 and about 0.5.

13. The structure of claim 9 further comprising:

an etch stop layer, wherein the bottom portion is in the etch stop layer; and

a dielectric layer over the etch stop layer, wherein the upper portion is in the dielectric layer.

14. The structure of claim 13 , wherein the conductive via further comprises a top portion over and joined to the upper portion, wherein in the plane view, the top portion is elongated.

15. A structure comprising:

a transistor comprising a source/drain region;

a gate stack on a side of the source/drain region;

a first conductive feature over and electrically coupling to the source/drain region, wherein the first conductive feature comprises:

an upper portion having a first edge, wherein the first edge is substantially straight; and

a lower portion having a second edge, wherein the second edge is curved, and wherein the upper portion and the lower portion are continuously connected to each other without distinguishable interface therebetween, wherein the lower portion has a first width, and the upper portion has a second width smaller than the first width, and both of the first width and the second width are measured in a direction that is parallel to a top surface of the source/drain region and parallel to a lengthwise direction of the gate stack.

16. The structure of claim 15 , wherein the lower portion is wider than at least a bottom part of the upper portion of the first conductive feature.

17. The structure of claim 15 , wherein the curved second edge has a top end and a bottom end, and wherein a largest width of the lower portion is at an intermediate level between the top end and the bottom end.

18. The structure of claim 15 further comprising:

an etch stop layer, wherein a part of the lower portion of the first conductive feature is in the etch stop layer; and

a dielectric layer over the etch stop layer, wherein the upper portion of the first conductive feature is in the dielectric layer.

19. The structure of claim 15 further comprising a second conductive feature between, and electrically interconnecting, the source/drain region and the first conductive feature.

20. The structure of claim 18 , wherein a widest part of the lower portion of the first conductive feature is in the etch stop layer.