Memory device having resistance switching element surrounding top electrode and integrated circuit device including the same
A memory device includes a substrate, an etch stop layer, a protective layer, and a resistance switching element. The substrate has a memory region and a logic region, and includes a metallization pattern therein. The etch stop layer is over the substrate, and has a first portion over the memory region and a second portion over the logic region. The protective layer covers the first portion of the etch stop layer. The protective layer does not cover the second portion of the etch stop layer. The resistance switching element is over the memory region, and the resistance switching element is electrically connected to the metallization pattern through the etch stop layer and the protective layer.
1. A memory device, comprising:
a bottom electrode;
a resistance switching element over the bottom electrode;
a top electrode over the resistance switching element, wherein the top electrode has a bottom surface, a top surface, and a sidewall extending from the bottom surface to the top surface of the top electrode, and the resistance switching element surrounds the top electrode and has a portion extending along the sidewall of the top electrode; and
a dielectric layer surrounding the bottom electrode, the resistance switching element, and the top electrode, wherein the bottom electrode has a portion between the resistance switching element and the dielectric layer.
2. The memory device of claim 1 , wherein the bottom electrode surrounds the resistance switching element and the top electrode.
3. The memory device of claim 1 , wherein a top surface of the bottom electrode is higher than the bottom surface of the top electrode.
4. The memory device of claim 1 , further comprising:
a spacer between the dielectric layer and the portion of the bottom electrode.
5. The memory device of claim 1 , further comprising:
a top electrode via connected to the top electrode; and
a passivation layer surrounding the top electrode via and covering a top surface of the bottom electrode and a top surface of the resistance switching element.
6. An integrated circuit device, comprising:
a substrate;
an interconnect layer over the substrate, wherein the interconnect layer comprises an interlayer dielectric layer and a first conductive feature surrounded by the interlayer dielectric layer;
a memory structure over the first conductive feature, wherein the memory structure comprises:
a bottom electrode over the first conductive feature, wherein the bottom electrode has a first portion extending along a top surface of the first conductive feature and a second portion extending from an end of the first portion in a direction away from the substrate;
a resistance switching element over the first portion of the bottom electrode; and
a top electrode over the resistance switching element; and
a second conductive feature over the top electrode of the memory structure.
7. The integrated circuit device of claim 6 , wherein a top of the second portion of the bottom electrode is free from coverage by the resistance switching element.
8. The integrated circuit device of claim 6 , wherein the resistance switching element has a first portion extending along a top surface of the first portion of the bottom electrode and a second portion extending along a sidewall of the second portion of the bottom electrode.
9. The integrated circuit device of claim 8 , wherein a top of the second portion of the resistance switching element is free from coverage by the top electrode.
10. The integrated circuit device of claim 6 , wherein the top electrode has a sidewall facing the second portion of the bottom electrode, and the resistance switching element spaces the sidewall of the top electrode from the second portion of the bottom electrode.
11. The integrated circuit device of claim 6 , wherein a width of the second conductive feature is less than a top width of the top electrode.
12. The integrated circuit device of claim 6 , wherein a bottom width of the bottom electrode is greater than a width of the first conductive feature.
13. An integrated circuit device, comprising:
a substrate;
an interconnect layer over the substrate, wherein the interconnect layer comprises an interlayer dielectric layer and a first conductive feature surrounded by the interlayer dielectric layer;
a memory structure over the first conductive feature, wherein the memory structure comprises:
a bottom electrode over the first conductive feature;
a resistance switching element over the bottom electrode; and
a top electrode over the resistance switching element, wherein a top of the resistance switching element is higher than a bottom surface of the top electrode; and
a second conductive feature over the top electrode.
14. The integrated circuit device of claim 13 , wherein a top of the bottom electrode is higher than the bottom surface of the top electrode.
15. The integrated circuit device of claim 14 , further comprising:
a passivation layer surrounding the second conductive feature, wherein the top of the bottom electrode and the top the resistance switching element are in contact with a bottom surface of the passivation layer.
16. The integrated circuit device of claim 15 , wherein a portion of a top surface of the top electrode is in contact with the bottom surface of the passivation layer.
17. The integrated circuit device of claim 13 , further comprising:
a spacer on a sidewall of the memory structure, wherein the resistance switching element and the top electrode are spaced apart from the spacer by the bottom electrode.
18. The integrated circuit device of claim 13 , wherein the bottom electrode has a U-shape.
19. The integrated circuit device of claim 13 , wherein the resistance switching element has a U-shape.
20. The memory device of claim 1 , wherein the portion of the resistance switching element forms a closed loop from a top view.