IP Library › Granted Patent US 11,363,299
Granted Patent B2
US 11,363,299 · App. 17/116,137 · Granted Jun 14, 2022

Encoding and decoding with merge mode and block partition index

Inventors: Jing Ya Li (Singapore, SG); Che Wei Kuo (Singapore, SG); Chong Soon Lim (Singapore, SG); Chu Tong Wang (Singapore, SG); Han Boon Teo (Singapore, SG); Hai Wei Sun (Singapore, SG); Kiyofumi Abe (Osaka, JP); Takahiro Nishi (Nara, JP); Tadamasa Toma (Osaka, JP); Yusuke Kato (Osaka, JP)
Assignee: Panasonic Intellectual Property Corporation Of America
H04N19/66H04N19/122H04N19/176H04N19/103H04N19/96
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Quick Facts
Patent No.
US 11,363,299
App. No.
17/116,137
Granted
Jun 14, 2022
Kind
B2
Abstract

An encoder includes circuitry and memory connected to the circuitry, and the circuitry, in operation: determines, based on a width and a height of a block, whether or not to disable a prediction mode in which the block is split along a partitioning line defined by a distance and an angle and then prediction is performed; and encodes the block with the prediction mode disabled or not disabled according to a result of the determination on whether or not to disable the prediction mode. Here, the distance is the shortest distance between the center of the block and the partitioning line, and the angle is an angle representing a direction from the center of the block toward the partitioning line in the shortest distance. The circuitry determines to disable the prediction mode when (i) a width-to-height ratio is at least 8 or (ii) a height-to-width ratio is at least 8.

Claims (14)

1. An encoder, comprising:

circuitry; and

memory connected to the circuitry,

wherein the circuitry, in operation,

determines a mode to be applied to a block from a plurality of merge modes based on a width of the block and a height of the block,

when the mode determined is a first mode, stores in a bitstream an index indicating a distance and an angle that define two partitions in the block, and encodes the block using the first mode, and

disables the first mode and storing of the index in the bitstream when (i) the width is 64 pixels and the height is 8 pixels or (ii) the height is 64 pixels and the width is 8 pixels.

2. A decoder, comprising:

circuitry; and

memory connected to the circuitry,

wherein the circuitry, in operation,

determines a mode to be applied to a block from a plurality of merge modes based on a width of the block and a height of the block,

when the mode determined is a first mode, obtains from a bitstream an index indicating a distance and an angle that define two partitions in the block, and decodes the block using the first mode, and

disables the first mode and obtaining of the index from the bitstream when (i) the width is 64 pixels and the height is 8 pixels or (ii) the height is 64 pixels and the width is 8 pixels.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 8, 2021
From: LI, JING YA; KUO, CHE WEI; LIM, CHONG SOON; WANG, CHU TONG; TEO, HAN BOON; SUN, HAI WEI; ABE, KIYOFUMI; NISHI, TAKAHIRO; TOMA, TADAMASA; KATO, YUSUKE
To: PANASONIC INTELLECTUAL PROPERTY CORPORATION OF AMERICA
Reel/Frame 056461/0118 →
Continuity (2)
Provisional Application 62947185 · Dec 12, 2019
Related Publication 20210195245A1 · Jun 24, 2021
Cited By (1)
US 12,294,696