Secure-aware bus system

1. An integrated-circuit device comprising:

a bus system, configured to carry bus transactions and to carry security-state signals for distinguishing between secure bus transactions and non-secure bus transactions;

a plurality of master components, each of the plurality of master components including circuitry, and each master component of the plurality of master components having a secure state and a non-secure state, wherein, when in the secure state, the respective master component initiates secure bus transactions, by outputting security-state signals to the bus system representative of secure bus transactions, and wherein, when in the non-secure state, the respective master component initiates non-secure bus transactions, by outputting security-state signals to the bus system representative of non-secure bus transactions;

a plurality of slave components; and

hardware filter logic,

wherein:

the hardware filter logic is configured to intercept bus transactions at an interception point within the bus system, the interception point being positioned within the bus system such that bus transactions from at least two of the master components pass the interception point, and such that bus transactions for at least two of the slave components pass the interception point; and

the hardware filter logic is configured, for each intercepted bus transaction, to use i) a slave address of the intercepted bus transaction, and ii) the security state of the intercepted bus transaction, to determine whether to allow the intercepted bus transaction, in accordance with a set of filtering rules, and is configured to block intercepted bus transaction that are determined not to be allowed.

2. The integrated-circuit device of claim 1 , wherein the filtering rules determine, for each pairing of master component and slave component, whether secure bus transactions initiated by the master component are allowed to be received by the slave component, and whether non-secure bus transactions initiated by the master component should be received by the slave component.

3. The integrated-circuit device of claim 1 , wherein the filtering rules are specified at a component level, such that, for each of the plurality of slave components, the hardware filter logic is configured to apply common filtering rules for each slave address assigned to the respective slave component.

4. The integrated-circuit device of claim 1 , wherein the filtering rules are such that all secure bus transactions, initiated by any of the master components, are allowed to reach all of the plurality of slave components, but, for a set of one or more of the slave components, no non-secure bus transactions, initiated by any of the master components, are allowed to reach the set of slave components.

5. The integrated-circuit device of claim 1 , wherein the filtering rules are different for different master components of the plurality of master components.

6. The integrated-circuit device of claim 1 , wherein the interception point is located at a bus arbiter, or is located at bridge between a first bus and a second bus in the bus system, or is located between a first layer and a second layer of the bus system.

7. The integrated-circuit device of claim 1 , wherein the hardware filter logic is configured to intercept bus transactions at one or more further interception points in the bus system.

8. The integrated-circuit device of claim 1 , wherein the filtering rules are such that, for each interception point, there is at least one respective slave address for which a secure bus transfer is allowed to pass the interception point and for which a non-secure bus transaction is not allowed to pass the interception point.

9. The integrated-circuit device of claim 1 , wherein a master component of the plurality of master components comprises a component core and a hardware security module, wherein the component core comprises a bus interface for initiating bus transactions without security-state signals, wherein the hardware security module is situated between the bus interface and the bus system, and wherein the hardware security module is switchable between a secure state and a non-secure state, and is configured to output a security-state signal onto the bus system for each bus transaction initiated by the component core, wherein the security-state signal indicates a secure bus transaction when the hardware security module is in the secure state, and indicates a non-secure bus transaction when the hardware security module is in the non-secure state.

10. The integrated-circuit device of claim 1 , wherein each of the slave components has a respective security state, and wherein the filtering rules additionally depend on the security states of the slaves components, such that the hardware filter logic is additionally configured to use one or more slave-component security states when determining whether to allow or block each intercepted bus transaction.

11. The integrated-circuit device of claim 1 , further comprising a memory, the memory comprising a secure region and a non-secure region, wherein the secure region is a first slave component of the plurality of components, and the non-secure region is a second slave component of the plurality of components.

12. The integrated-circuit device of claim 1 , wherein the filtering rules further depend on whether the intercepted bus transaction is a data read, a data write, or an instruction fetch transaction, and wherein the hardware filter logic is configured to determine whether each intercepted bus transaction is a data read, a data write, or an instruction fetch transaction.

13. The integrated-circuit device of claim 1 , comprising a security protection unit which provides a register interface, accessibly over the bus system, for switching one or more of the master components and/or one or more of the slave components between a secure state and a non-secure state.

14. The integrated-circuit device of claim 1 , wherein the bus system comprises main bus and a peripheral bus, wherein the main bus comprises a main-bus security-state signal line for carrying the security-state signal, and wherein the peripheral bus comprises a peripheral-bus security-state signal line for carrying the security-state signal to one or more peripherals attached to the peripheral bus.

15. A method of operating an integrated-circuit device, wherein the integrated-circuit device comprises:

a bus system for carrying bus transactions and for carrying security-state signals for distinguishing between secure bus transactions and non-secure bus transactions;

a plurality of master components, each of the plurality of master components including circuitry, and each master component of the plurality of master components having a secure state and a non-secure state, wherein, when in the secure state, the respective master component initiates secure bus transactions, by outputting security-state signals to the bus system representative of secure bus transactions, and wherein, when in the non-secure state, the respective master component initiates non-secure bus transactions, by outputting security-state signals to the bus system representative of non-secure bus transactions; and

a plurality of slave components,

the method comprising:

the bus system carrying secure bus transactions and non-secure bus transactions;

intercepting bus transactions at an interception point within the bus system, the interception point being positioned within the bus system such that bus transactions from at least two of the master components pass the interception point, and such that bus transactions for at least two of the slave components pass the interception point;

using the address of an intercepted bus transaction and the security state of the intercepted bus transaction to determine whether to allow the intercepted bus transaction, in accordance with a set of filtering rules; and

blocking the intercepted bus transaction when the intercepted bus transaction is determined not to be allowed.