Memory structure with doping-induced leakage paths

1. A method, comprising:

receiving a workpiece comprising:

a gate structure comprising a gate dielectric layer,

a dielectric layer over the gate structure,

a gate contact disposed in the dielectric layer and directly over the gate structure, the gate contact being physically and electrically coupled to the gate structure, and

a source/drain contact adjacent the gate contact and disposed in the dielectric layer;

after receiving the workpiece, implanting the dielectric layer with a dopant; and

applying a voltage across the gate contact and the source/drain contact to form a leakage path through the dielectric layer,

wherein the voltage is equal to or greater than a breakdown voltage of the dielectric layer between the gate contact and the source/drain contact, but is smaller than a breakdown voltage of the gate dielectric layer.

2. The method of claim 1 , wherein the implanting of the dielectric layer reduces a breakdown voltage of the dielectric layer between the gate contact and the source/drain contact.

3. The method of claim 1 , wherein the implanting of the dielectric layer comprises a dose between about 5×10 14 atoms/cm 2 and about 1×10 15 atoms/cm 2 .

4. The method of claim 1 , wherein the implanting of the dielectric layer comprises an implantation energy between about 5 keV and about 30 keV.

5. The method of claim 1 , wherein the dopant is an element of group 4A of the periodic table.

6. The method of claim 1 , wherein the dopant comprises germanium or tin.

7. A semiconductor device, comprising:

a gate structure;

a source/drain feature adjacent the gate structure;

a dielectric layer disclosed over the gate structure and the source/drain feature;

a gate contact disposed in the dielectric layer and directly over the gate structure, the gate contact being physically and electrically coupled to the gate structure;

a source/drain contact disposed in the dielectric layer and over the source/drain feature; and

a leakage path between the gate contact and the source/drain contact to couple the gate contact and the source/drain contact,

wherein the dielectric layer is doped with germanium or tin.

8. The semiconductor device of claim 7 ,

wherein the gate structure comprises a gate dielectric layer,

wherein a breakdown voltage of the gate dielectric layer is greater than a breakdown voltage of the dielectric layer between the gate contact and the source/drain contact.

9. The semiconductor device of claim 7 , wherein the dielectric layer comprises tetraethylorthosilicate (TEOS) oxide, undoped silicate glass (USG), borophosphosilicate glass (BPSG), fluorosilicate glass (FSG), phosphosilicate glass (PSG), or boron doped silicon glass (BSG).

10. The semiconductor device of claim 7 , wherein a breakdown voltage of the dielectric layer between the gate contact and the source/drain contact is between about 2 volts and about 3 volts.

11. The semiconductor device of claim 7 , wherein a concentration of the dopant in the dielectric layer is between about 5×10 14 atoms/cm 3 and about 1×10 15 atoms/cm 3 .

12. The semiconductor device of claim 7 , wherein the leakage path comprises materials of the gate contact or materials of the source/drain contact.

13. The semiconductor device of claim 7 , wherein the leakage path physically extends through a portion of the dielectric layer.

14. A one-time programmable (OTP) memory device, comprising:

an active region;

a first gate structure and a second gate structure over the active region, the first gate structure comprising a gate dielectric layer;

a dielectric layer disclosed over the first gate structure and the second gate structure;

a first source/drain contact disposed between the first gate structure and the second gate structure;

a second source/drain contact spaced apart from the first source/drain contact by the second gate structure; and

a first gate contact disposed directly on and electrically coupled to the first gate structure, the first gate contact being physically and electrically coupled to the first gate structure,

wherein a portion of the first source/drain contact, a portion of the second source/drain contact, and the first gate contact are disposed within the dielectric layer,

wherein the dielectric layer is doped with a germanium or tin, and

wherein a breakdown voltage of the gate dielectric layer is greater than a breakdown voltage of the dielectric layer.

15. The OTP memory device of claim 14 , wherein a breakdown voltage of the dielectric layer between the first gate contact and the first source/drain contact is between about 2 volts and about 3 volts.

16. The OTP memory device of claim 14 , wherein a concentration of the dopant in the dielectric layer is between about 5×10 14 atoms/cm 3 and about 1×10 15 atoms/cm 3 .

17. The OTP memory device of claim 14 , wherein the second source/drain contact is coupled to a bit line by way of a source/drain contact via.

18. The OTP memory device of claim 14 , further comprising:

a leakage path between the first gate contact and the first source/drain contact; and

a second gate contact disposed over and electrically coupled to the second gate structure,

wherein the second gate contact is disposed within the dielectric layer,

wherein a portion of the dielectric layer between the second gate contact and the first source/drain contact is free of a leakage path.

19. The OTP memory device of claim 18 ,

wherein the first gate contact is coupled to a program word line,

wherein the second gate contact is coupled to a read word line,

wherein the first gate structure and the second gate structure extend lengthwise along a first direction,

wherein the program word line and the read word line extend lengthwise along a second direction perpendicular to the first direction.