Method for LUT-free memory repair
View Patent ↗Various embodiments of the present disclosure are directed towards a method for memory repair using a lookup table (LUT)-free dynamic memory allocation process. An array of memory cells having a plurality of rows and a plurality of columns is provided. Further, each memory cell of the array has multiple data states and a permanent state. One or more abnormal memory cells is/are identified in a row of the array and, in response to identifying an abnormal memory cell, the abnormal memory cell is set to the permanent state. The abnormal memory cells include failed memory cells and, in some embodiments, tail memory cells having marginal performance. During a read or write operation on the row, the one or more abnormal memory cells is/are identified by the permanent state and data is read from or written to a remainder of the memory cells while excluding the abnormal memory cell(s).
1. A method comprising:
providing an array of memory cells having a plurality of rows and a plurality of columns, wherein the plurality of rows comprises a first row;
identifying individual states of memory cells of the array in the first row, wherein the states are respectively a first data state, a second data state, and a permanent state;
allocating memory cells identified respectively with the first and second data states into a logical word while excluding a memory cell identified with the permanent state, wherein the memory cell identified with the permanent state is between the memory cells identified respectively with the first and second data states; and
reading the logical word from or writing the logical word to the memory cells allocated to the logical word.
2. The method according to claim 1 , wherein the first row is configured to store a first physical word and a second physical word, wherein the first and second physical words share a common size greater than that of the logical word, and wherein the logical word is localized to memory cells corresponding to the first physical word.
3. The method according to claim 1 , wherein the allocating is performed from left to right along the first row of the array.
4. The method according to claim 1 , wherein the identifying comprises:
biasing the memory cells of the array in the first row to generate individual read currents through the memory cells, wherein read currents are different for the first data state, the second data state, and the permanent state; and
comparing the read currents to multiple reference currents to identify the individual states of the memory cells of the array in the first row.
5. The method according to claim 1 , wherein the logical word comprises a data word and an error-correcting code (ECC) code, and wherein the method further comprises:
performing an ECC operation to generate or decode the ECC code, wherein the ECC operation and the allocating are performed by the same circuit.
6. The method according to claim 1 , wherein the logical word comprises a data word and an error-correcting code (ECC) code, and wherein the method further comprises:
performing an ECC operation on the logical word to generate or decode the ECC code, wherein the ECC operation and the allocating are independent of each other.
7. The method according to claim 1 , further comprising:
receiving an address for the reading or the writing, wherein the address identifies a second row of the plurality of rows;
looking the second row up in a lookup table to determine whether the second row is mapped to a redundant row; and
determining that the second row is mapped to the redundant row in the lookup table, wherein the redundant row is the first row.
8. The method according to claim 1 , further comprising:
identifying a tail memory cell in the first row, wherein the tail memory cell falls within a design specification but is at a boundary of the design specification; and
setting the tail memory cell to the permanent state, wherein the memory cell identified with the permanent state is the tail memory cell.
9. A memory device comprising:
a memory core comprising:
an array of memory cells having a plurality of rows and a plurality of columns, wherein each memory cell of the array has a first data state, a second data state, and a permanent state, and wherein the plurality of rows comprises a first row; and
a sense amplifier circuit configured to identify a memory cell of the first row as being in the permanent state and to identify memory cells of the first row as being respectively in the first and second data states, wherein the memory cell in the permanent state is between the memory cells respectively in the first and second data states; and
an allocation circuit configured to allocate the memory cells identified as respectively being in the first and second data states to a logical word while excluding the memory cell identified as being in the permanent state;
wherein the memory core is configured to read or write the logical word respectively from or to the memory cells allocated to the logical word.
10. The memory device according to claim 9 , wherein the allocation circuit is configured to change the memory cells allocated to the logical word in response to a memory cell previously allocated to the logical word being set to the permanent state.
11. The memory device according to claim 9 , wherein the sense amplifier circuit comprises a sense amplifier configured to:
compare a read current through a memory cell of the array to a reference current;
identify the memory cell as being in the permanent state in response to the read current exceeding the reference current, and as being in the first or second data state in response to the read current being below the reference current.
12. The memory device according to claim 9 , wherein the logical word comprises a data word and an error-correcting code (ECC) code, and wherein the memory device further comprises:
an ECC circuit configured to generate or decode the ECC code during the read or write, wherein the ECC circuit is independent of and spaced from the allocation circuit.
13. The memory device according to claim 9 , wherein the logical word comprises a data word and an error-correcting code (ECC) code, and wherein the allocation circuit is further configured to generate or decode the ECC code during the read or write.
14. The memory device according to claim 9 , wherein each of the memory cells of the array comprises a bottom electrode, a top electrode, and an insulator between the bottom and top electrodes, and wherein the insulator of the memory cell identified in the permanent state is irreversibly broken down.
15. The memory device according to claim 9 , wherein the memory cells are resistive random-access memory (RRAM) cells, magnetoresistive random-access memory (MRAM) cells, ferroelectric random-access memory (FeRAM) cells, or one selector-one resistor (1S1R) phase change memory (PCM) cells.
16. A method comprising:
providing an array of memory cells having a plurality of rows, a plurality of data columns, and a redundant column, wherein each memory cell of the array has a first data state, a second data state, and a permanent state;
identifying an abnormal memory cell in a first row of the plurality of rows and at a first data column of the plurality of data columns;
setting the abnormal memory cell to the permanent state;
allocating memory cells from the first row to a logical word, wherein the logical word includes memory cells from the plurality of data columns and the redundant column while excluding memory cells set to the permanent state; and
reading the logical word from or writing the logical word to the memory cells allocated to the logical word.
17. The method according to claim 16 , wherein the abnormal memory cell is a failed memory cell falling outside of a design specification.
18. The method according to claim 16 , wherein the abnormal memory cell is a tail memory cell falling within a design specification, but at a boundary of the design specification.
19. The method according to claim 18 , wherein the method further comprises:
determining a number of redundant memory cells unused in the first row;
wherein the determined number is greater than zero, and wherein the abnormal memory cell is set to the permanent state in response to determining the number of redundant memory cells is greater than zero.
20. The method according to claim 16 , wherein the setting of the abnormal memory cell to the permanent state comprises forcing the abnormal memory cell to have a lower resistance than resistances of memory cells respectively in the first data state and the second data state.