Semiconductor manufacturing
View Patent ↗Short channel, horizontal gate-all-around (GAA) nanostructure (e.g., nanosheet, nanowire, or the like) transistors, methods of manufacturing and devices formed with the GAA transistors are disclosed herein. According to some methods, the GAA transistors are formed with a guard band for preventing diffusion of APT doping into the channel region, with shallow source/drain depths, and/or with epitaxial growth of the device channel regions after well and APT implantation in the substrate. As such, the GAA transistors are formed to mitigate issues such as bottom sheet voltage threshold (Vt) shift, junction leakage, APT dopant out-diffusion, well proximity effect, APT implant contamination that may be induced by anti-punch through (APT) doping diffusion during fabrication of gate all-around (GAA) transistors. The GAA transistors and methods of manufacturing, however, may be utilized in a wide variety of ways, and may be integrated into a wide variety of devices and technologies.
1. A method comprising:
depositing a first layer of a first material over a semiconductor substrate, wherein the first material comprises silicon germanium;
depositing a first layer of a second material over the first layer of the first material;
depositing a second layer of the first material over the first layer of the second material, a thickness of the first layer of the first material being greater than a thickness of the second layer of the first material;
depositing a second layer of the second material over the second layer of the first material;
removing the first material from between the first layer of the second material and the semiconductor substrate and from between the first layer of the second material and the second layer of the second material to form a first nanostructure spaced apart from the semiconductor substrate by a first spacing and to form a second nanostructure spaced apart from the first nanostructure by a second spacing, the second spacing being less than the first spacing;
depositing a gate dielectric layer to surround the first and second nanostructures;
depositing a gate electrode around the gate dielectric layer;
etching a first opening through the first layer of the first material to a first depth;
epitaxially growing a first source/drain region in the first opening, wherein the depositing the gate electrode further comprises forming a bottom of the gate electrode to be closer to the semiconductor substrate than the first source/drain region;
implanting anti-punch through dopants into the semiconductor substrate; and
causing a concentration gradient of the anti-punch through dopants to extend into the first layer but not into the second layer.
2. The method of claim 1 , wherein the first spacing is between about 1.1 times to about 2 times the second spacing.
3. The method of claim 2 , wherein the first spacing is between about 6 nm and about 20 nm and the second spacing is between about 5 nm and about 12 nm.
4. The method of claim 2 , further comprising, prior to the depositing the first layer of the first material, performing the implanting the anti-punch through dopant into the semiconductor substrate.
5. The method of claim 4 , wherein the etching the first opening etches the first opening into the semiconductor substrate.
6. A method, comprising:
implanting anti-punch through dopants into a semiconductor substrate;
forming a first layer comprising a first semiconductor material over the semiconductor substrate to a first thickness;
forming a second layer comprising a second semiconductor material over the first layer to a second thickness, the second semiconductor material being different from the first semiconductor material and the first thickness being greater than the second thickness;
heating the semiconductor substrate, wherein the heating the semiconductor substrate causes a concentration gradient of the anti-punch through dopants to extend into the first layer but not into the second layer;
removing the first semiconductor material from between the second semiconductor material and the semiconductor substrate to form a first nanostructure spaced apart from the semiconductor substrate by a first distance;
depositing a gate dielectric layer to surround the first nanostructure; and
forming a gate electrode, wherein at least a first portion of the gate electrode is formed between the semiconductor substrate and the first nanostructure.
7. The method of claim 6 , wherein the first thickness is between about 6 nm and about 20 nm and the second thickness is between about 5 nm and about 12 nm.
8. The method of claim 7 , further comprising:
forming a third layer over the second layer to a third thickness, the third layer comprising the first semiconductor material, the third thickness being less than the first thickness;
forming a fourth layer over the third layer to a fourth thickness, the fourth layer comprising the second semiconductor material, the fourth thickness being less than the first thickness; and
removing the first semiconductor material from between the fourth layer and the second layer to form a second nanostructure spaced apart from the first nanostructure by a second distance, the second distance being less than the first distance.
9. The method of claim 8 , wherein the forming the gate electrode comprises forming a second portion of the gate electrode between the first nanostructure and the second nanostructure, a first height of the first portion of the gate electrode being greater than a second height of the second portion of the gate electrode.
10. The method of claim 9 , wherein the first height of the first portion of the gate electrode is between about 1.1 times to about 2.0 times the second height of the second portion of the gate electrode.
11. The method of claim 8 , further comprising forming a first source/drain region, the first source/drain region extending into the semiconductor substrate.
12. The method of claim 8 , further comprising forming a first source/drain region, a bottom of the first source/drain region being formed further from the semiconductor substrate than the first portion of the gate electrode.
13. A method of manufacturing a semiconductor device, the method comprising:
forming a stack of semiconductor nanostructures over a substrate;
forming a gate dielectric surrounding each semiconductor nanostructure;
forming a gate electrode surrounding each semiconductor nanostructure within the stack of semiconductor nanostructures, wherein after the forming the gate electrode a first height of the gate electrode between the substrate and a bottommost nanostructure of the stack of semiconductor nanostructures is greater than a second height of the gate electrode between the bottommost nanostructure and another nanostructure of the stack of semiconductor nanostructures, wherein the first height is between about 1.1 times to about 2.0 times the second height;
forming a source/drain region, wherein a bottom of the source/drain region is located further from the substrate than a bottom of the gate dielectric;
implanting anti-punch through dopants into the semiconductor substrate; and
using heat to extend the anti-punch through dopants into a first layer of the stack but not into a second layer of the stack.
14. The method of claim 13 , further comprising forming a source/drain region, wherein the source/drain region extends into the substrate.
15. The method of claim 13 , wherein the first height is between about 6 nm and about 20 nm and the second height is between about 5 nm and about 12 nm.
16. The method of claim 13 , further comprising forming an anti-punch through dopant region located within the substrate but not within the stack of semiconductor nanostructures.
17. The method of claim 1 , wherein the implanting the anti-punch through dopants uses an implantation dosage with a concentration of between about 1E13/cm 2 and about 1.5E14/cm 2 .
18. The method of claim 1 , wherein the implanting the anti-punch through dopants implant a p-type dopant to a concentration of between about 3E13/cm 2 and about 5E14/cm 2 .
19. The method of claim 13 , wherein the implanting the anti-punch through dopants implant a n-type dopant to a concentration of between about 3E13/cm 2 and about 5E14/cm 2 .
20. The method of claim 13 , wherein the implanting the anti-punch through dopants implant a p-type dopant to a concentration of between about 3E13/cm 2 and about 5E14/cm 2 .