IP Library › Granted Patent US 11,368,686
Granted Patent B2
US 11,368,686 · App. 17/194,781 · Granted Jun 21, 2022

Encoder and decoder

Inventors: Tadamasa Toma (Osaka, JP); Takahiro Nishi (Nara, JP); Kiyofumi Abe (Osaka, JP)
Assignee: PANASONIC INTELLECTUAL PROPERTY CORPORATION OF AMERICA
H04N19/119H04N19/105H04N19/117H04N19/159H04N19/174H04N19/52H04N19/82
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Quick Facts
Patent No.
US 11,368,686
App. No.
17/194,781
Granted
Jun 21, 2022
Kind
B2
Abstract

An encoder includes circuitry and memory connected to the circuitry. The circuitry, in operation: splits one picture included in pictures into areas, intra encodes the entirety of an area among the areas; and switches areas to be intra encoded for each picture included in the pictures. In at least one of (i) generation of a reference pixel in inter prediction or (ii) loop filtering, only pixels in the area intra encoded or pixels in an area which precedes the area intra encoded in coding order are used among pixels included in the pictures.

Claims (52)

1. An encoder, comprising:

circuitry; and

memory connected to the circuitry,

wherein, in operation, the circuitry:

for each of the plurality of pictures, (i) splits the picture into a plurality of areas and (ii) intra encodes an entirety of any area among the plurality of areas obtained by splitting the picture,

positions of the intra encoded areas in the plurality of pictures are a cycle of positions which are cyclically different between the plurality of pictures,

each of the plurality of pictures includes the intra encoded area and one or more areas which precede the intra encoded area in coding order, and

in at least one of (i) generation of reference pixels in inter prediction or (ii) loop filtering which are performed for a current block included in one of the plurality of areas, only pixels in the intra encoded area and pixels in the one or more areas are used, the intra encoded area and the one or more areas which precede the intra encoded area being two or more areas which are respectively included in two or more pictures included in the plurality of pictures and which have been encoded.

2. The encoder according to claim 1 ,

wherein each of the plurality of areas is a slice.

3. The encoder according to claim 1 ,

wherein each of the plurality of areas is an area obtained by splitting the picture in a vertical direction.

4. The encoder according to claim 3 ,

wherein each of the plurality of areas is the area obtained by splitting the picture in the vertical direction; and

the circuitry further performs encoding based on a coding unit which is a slice or a tile.

5. The encoder according to claim 1 ,

wherein the inter prediction is either a method of correcting a motion vector for each pixel based on gradient information of values of neighboring pixels calculated for the pixel, or a method of correcting a motion vector for each sub-pixel based on gradient information of values of neighboring pixels calculated for the sub-pixel.

6. The encoder according to claim 1 ,

wherein the inter prediction is a method of performing motion estimation in a decoding process, based on a motion vector as a merge candidate, and correcting a motion vector for each block.

7. The encoder according to claim 1 ,

wherein the loop filtering is deblocking filtering.

8. The encoder according to claim 1 ,

wherein the loop filtering is a method of performing filtering by selecting one of a plurality of sets of filter coefficients encoded for each of blocks in a stream.

9. The encoder according to claim 1 ,

wherein the circuitry encodes information for identifying, in the plurality of pictures, a picture whose leading area in coding order among a plurality of areas is to be intra encoded.

10. The encoder according to claim 1 ,

wherein when the plurality of pictures are to be encoded in a mode in which decoding in units of a parallel processing unit is valid, the circuitry determines a size of each of the plurality of areas in a vertical direction or a horizontal direction, based on a size of the parallel processing unit.

11. A decoder, comprising:

circuitry; and

memory connected to the circuitry,

wherein, in operation, the circuitry:

for each of the plurality of pictures, (i) splits the picture into a plurality of areas and (ii) intra decodes an entirety of any area among the plurality of areas obtained by splitting the picture,

positions of the intra decoded areas in the plurality of pictures are a cycle of positions which are cyclically different between the plurality of pictures,

each of the plurality of pictures includes the intra decoded area and one or more areas which precede the intra decoded area in coding order, and

in at least one of (i) generation of reference pixels in inter prediction or (ii) loop filtering which are performed for a current block included in one of the plurality of areas, only pixels in the intra decoded area and pixels in the one or more areas are used, the intra decoded area and the one or more areas which precede the intra decoded area being two or more areas which are respectively included in two or more pictures included in the plurality of pictures and which have been decoded.

12. The decoder according to claim 11 ,

wherein each of the plurality of areas is a slice.

13. The decoder according to claim 11 ,

wherein each of the plurality of areas is an area obtained by splitting the picture in a vertical direction.

14. The decoder according to claim 13 ,

wherein each of the plurality of areas is the area obtained by splitting the picture in the vertical direction; and

the circuitry further performs encoding based on a coding unit which is a slice or a tile.

15. The decoder according to claim 11 ,

wherein the inter prediction is either a method of correcting a motion vector for each pixel based on gradient information of values of neighboring pixels calculated for the pixel, or a method of correcting a motion vector for each sub-pixel based on gradient information of values of neighboring pixels calculated for the sub-pixel.

16. The decoder according to claim 11 ,

wherein the inter prediction is a method of performing motion estimation in a decoding process, based on a motion vector as a merge candidate, and correcting a motion vector for each block.

17. The decoder according to claim 11 ,

wherein the loop filtering is deblocking filtering.

18. The decoder according to claim 11 ,

wherein the loop filtering is a method of performing filtering by selecting one of a plurality of sets of filter coefficients decoded for each of blocks in a stream.

19. The decoder according to claim 11 ,

wherein the circuitry decodes information for identifying, in the plurality of pictures, a picture whose leading area in decoding order among a plurality of areas is to be intra decoded.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 13, 2021
From: TOMA, TADAMASA; NISHI, TAKAHIRO; ABE, KIYOFUMI
To: PANASONIC INTELLECTUAL PROPERTY CORPORATION OF AMERICA
Reel/Frame 056843/0385 →
Continuity (3)
Continuation PCTJP2019035776 · Sep 11, 2019
Provisional Application 62729801 · Sep 11, 2018
Related Publication 20210211661A1 · Jul 8, 2021