Management of the untranslated to translated code steering logic in a dynamic binary translation based processor

1. A method comprising:

monitoring, by a translation table (TT) controller associated with a binary translation based (BT) processor, execution of a second code translated from a first code; and

updating, based on a performance metric of the execution, an attribute value of a TT entry, the attribute value comprising at least one of:

a TT hit count attribute value representing a number of times that a mapping has been used to translate the first code to the second code;

a loop attribute value indicating whether there are instruction loops in the first code;

a dynamic execution count attribute value representing a number of instructions in the first code divided by a number of conditional branches in the first code;

a gear level attribute value representing a number of rounds of optimization in translating the first code to the second code; or

a prefetch attribute value indicating whether the TT entry is prefetched from a full list of mappings stored in memory.

2. The method of claim 1 , further comprising:

selecting, based on the attribute value, an eviction victim entry from a plurality of entries in the translation table; and

evicting the eviction victim entry from the translation table.

3. A system comprising:

a memory to store a first code at a first address and a second code, translated from the first code, at a second address;

a processor comprising an instruction execution circuit to execute the second code; and

a translation table (TT) controller coupled to a translation table to store a TT entry comprising:

a mapping between the first address and the second address; and

an attribute field comprising an attribute value associated with execution of the second code, wherein the attribute value comprises at least one of:

a TT hit count attribute value representing a number of times that the mapping has been used to translate the first code to the second code;

a loop attribute value indicating whether there are instruction loops in the first code;

a dynamic execution count attribute value representing a number of instructions in the first code divided by a number of conditional branches in the first code;

a gear level attribute value representing a number of rounds of optimization in translating the first code to the second code; or

a prefetch attribute value indicating whether the TT entry is prefetched from a full list of mappings stored in the memory; and

the TT controller is to:

monitor an execution of the second code by the instruction execution circuit; and

update, based on a performance metric of the execution, the attribute value of the TT entry.

4. The system of claim 3 , wherein the processor further comprises a binary translator to:

translate the first code to the second code;

store the second code at the second address of the memory; and

generate the TT entry stored in the translation table.

5. The system of claim 3 , wherein the first code is specified according to a first instruction set architecture, and wherein the second code is specified according to one of the first instruction set architecture or a second instruction set architecture.

6. The system of claim 3 , wherein the TT controller is further to:

identify, using the instruction execution circuit, the first code to be executed;

search the translation table to determine whether the TT entry comprises the mapping between the first code and the second code; and

responsive to determining that TT entry comprises the mapping, cause the instruction execution circuit to execute the second code.

7. The system of claim 3 , wherein the TT controller further comprises a replacement policy circuit to:

select, based on the attribute value, an eviction victim entry from a plurality of entries in the translation table; and

evict the eviction victim entry from the translation table.

8. The system of claim 7 , wherein the replacement policy circuit to designate, based on at least one of TT hit count attribute values, loop attribute values, dynamic execution count attribute values, gear level attribute values, prefetch attribute values associated with the plurality of entries, a first entry as the eviction victim entry.

9. A processor comprising:

an instruction execution circuit to execute a second code stored at a second address of a memory, wherein the second code is translated from a first code stored at a first address of the memory; and

a translation table (TT) controller coupled to a translation table to store a TT entry comprising:

a mapping between the first address and the second address; and

an attribute field comprising an attribute value associated with execution of the second code, wherein the attribute value comprises at least one of:

a TT hit count attribute value representing a number of times that the mapping has been used to translate the first code to the second code;

a loop attribute value indicating whether there are instruction loops in the first code;

a dynamic execution count attribute value representing a number of instructions in the first code divided by a number of conditional branches in the first code;

a gear level attribute value representing a number of rounds of optimization in translating the first code to the second code; or

a prefetch attribute value indicating whether the TT entry is prefetched from a full list of mappings stored in the memory; and

the TT controller is to:

monitor an execution of the second code by the instruction execution circuit; and

update, based on a performance metric of the execution, the attribute value of the TT entry.

10. The processor of claim 9 , further comprising a binary translator circuit to:

translate the first code to the second code;

store the second code at the second address of the memory; and

generate the TT entry stored in the translation table.

11. The processor of claim 9 , wherein the first code is specified according to a first instruction set architecture, and wherein the second code is specified according to one of the first instruction set architecture or a second instruction set architecture.

12. The processor of claim 9 , wherein the TT controller is further to:

identify, using the instruction execution circuit, the first code to be executed;

search the translation table to determine whether the TT entry comprises the mapping between the first code and the second code; and

responsive to determining that TT entry comprises the mapping, cause the instruction execution circuit to execute the second code.

13. The processor of claim 9 , wherein the TT controller further comprises a replacement policy circuit to:

select, based on the attribute value, an eviction victim entry from a plurality of entries in the translation table; and

evict the eviction victim entry from the translation table.

14. The processor of claim 13 , wherein the replacement policy circuit to designate, based on TT hit count attribute values associated with the plurality of entries, a first entry in the translation table as the eviction victim entry.

15. The processor of claim 13 , wherein the replacement policy circuit to determine, based on loop attribute values associated with the plurality of entries, a first entry in the translation table as the eviction victim entry.

16. The processor of claim 13 , wherein the replacement policy circuit to determine, based on dynamic execution count attribute values associated with the plurality of entries, a first entry in the translation table as the eviction victim entry.

17. The processor of claim 13 , wherein the replacement policy circuit to determine, based on gear level attribute values associated with the plurality of entries, a first entry in the translation table as the eviction victim entry.

18. The processor of claim 13 , wherein the replacement policy circuit is to determine, based on prefetch attribute values associated with the plurality of entries, a first entry in the translation table as the eviction victim entry.