Transceiver, bridge chip, semiconductor storage device, and method
According to one embodiment, a transceiver includes a sampler, a pipeline, and a transmission circuit. The sampler takes a data signal received from a host at a timing based on a data strobe signal received from the host. The pipeline transfers the data signal taken by the sampler using at least a clock signal, different from the data strobe signal, as a drive signal. The transmission circuit acquires and transmits a data signal having passed through the pipeline.
1. A transceiver comprising:
a sampler that takes a data signal received from a host at a timing based on a data strobe signal received from the host;
a pipeline that transfers the data signal taken by the sampler using a drive signal, the pipeline using, during a first period, the data strobe signal as the drive signal, and using, during a second period different from the first period, a clock signal, different from the data strobe signal, as the drive signal; and
a transmission circuit that acquires and transmits the data signal having passed through the pipeline.
2. The transceiver according to claim 1 , wherein
the first period is a period when the data strobe signal is input, and
the transceiver further comprises:
a supply circuit that supplies the data strobe signal to the pipeline as the drive signal during the first period, and supplies the clock signal to the pipeline as the drive signal during the second period after the first period.
3. The transceiver according to claim 2 , wherein
the supply circuit determines the end of the input of the data strobe signal based on a count of a number of times the data strobe signal is toggled.
4. The transceiver according to claim 2 , wherein
the supply circuit determines the end of the input of the data strobe signal based on sampling of the data strobe signal.
5. The transceiver according to claim 1 , wherein
the sampler includes a first-in first-out (FIFO) memory, stores the data signal taken at a timing based on the data strobe signal into the FIFO memory, and inputs the data signal stored in the FIFO memory to the pipeline at a timing based on the clock signal, and
the pipeline transfers the data signal using the clock signal.
6. The transceiver according to claim 5 , wherein
a frequency of the clock signal is higher than a frequency of the data strobe signal.
7. The transceiver according to claim 6 , further comprising
an oscillator circuit that oscillates the clock signal.
8. The transceiver according to claim 7 , further comprising
a correction circuit that corrects a frequency of the clock signal based on a comparison between the data strobe signal and the clock signal.
9. The transceiver according to claim 1 , further comprising
an oscillator circuit that oscillates the clock signal.
10. The transceiver according to claim 9 , further comprising
a correction circuit that corrects a frequency of the clock signal based on a comparison between the data strobe signal and the clock signal.
11. A bridge chip which is electrically connected to a host and a memory chip and executes data transfer between the host and the memory chip, the bridge chip comprising:
a first interface that receives a data signal and a data strobe signal from the host;
a sampler that takes the data signal at a timing based on the data strobe signal;
a pipeline that transfers the data signal taken by the sampler using a drive signal, the pipeline using, during a first period, the data strobe signal as the drive signal, and using, during a second period different from the first period, a clock signal, different from the data strobe signal, as the drive signal;
a transmission circuit that acquires and transmits the data signal having passed through the pipeline; and
a second interface that transmits the data signal transmitted by the transmission circuit to the memory chip.
12. A semiconductor storage device comprising:
a bridge chip that is electrically connectable to a host and is capable of receiving a signal from the host; and
a memory chip electrically connected to the bridge chip, wherein
the bridge chip includes:
a sampler that takes a data signal received from the host at a timing based on a data strobe signal received from the host;
a pipeline that transfers the data signal taken by the sampler using a drive signal, the pipeline using during a first period, the data strobe signal as the drive signal, and using, during a second period different from the first period, a clock signal, different from the data strobe signal, as the drive signal; and
a transmission circuit that acquires and transmits the data signal having passed through the pipeline.
13. The semiconductor storage device according to claim 12 , wherein
the first period is a period when the data strobe signal is input, and
the semiconductor storage device further comprises:
a supply circuit that supplies the data strobe signal to the pipeline as the drive signal during the first period, and supplies the clock signal to the pipeline as the drive signal during the second period after the first period.
14. The semiconductor storage device according to claim 12 , wherein
the sampler includes a first-in first-out (FIFO) memory, stores the data signal taken at a timing based on the data strobe signal in the FIFO memory, and inputs the data signal stored in the FIFO memory to the pipeline at a timing based on the clock signal, and
the pipeline transfers the data signal using the clock signal.
15. The semiconductor storage device according to claim 14 , wherein
a frequency of the clock signal is higher than a frequency of the data strobe signal.
16. The semiconductor storage device according to claim 15 , further comprising
an oscillator circuit that oscillates the clock signal.
17. The semiconductor storage device according to claim 16 , further comprising
a correction circuit that corrects a frequency of the clock signal based on a comparison between the data strobe signal and the clock signal.
18. The semiconductor storage device according to claim 12 , further comprising
an oscillator circuit that oscillates the clock signal.
19. The semiconductor storage device according to claim 18 , further comprising
a correction circuit that corrects a frequency of the clock signal based on a comparison between the data strobe signal and the clock signal.
20. A method comprising:
taking a data signal received from a host at a timing based on a data strobe signal received from the host;
transferring the taken data signal via a pipeline using during a first period, the data strobe signal as a drive signal, and using, during a second period different from the first period, a clock signal, different from the data strobe signal, as the drive signal; and
acquiring and transmitting the data signal that has passed through the pipeline.