Unified address space for multiple links
There is disclosed in one example an apparatus, including: a plurality of interconnects to communicatively couple an accelerator device to a host device; and an address translation module (ATM) to provide address mapping between host-physical address (HPA) and guest-physical address (GPA) spaces for the accelerator device, wherein the plurality of devices share a common GPA domain and wherein address mapping is to be associated with only one of the plurality of interconnects.
1. An apparatus, comprising:
a plurality of physical interconnects to communicatively couple an accelerator device to a host device, wherein the host device is to execute software; and
an address translation module (ATM) to provide address mapping between host-physical address (HPA) and guest-physical address (GPA) spaces for the accelerator device, wherein the plurality of physical interconnects share a common GPA domain and wherein address mapping is to be associated with only one of the plurality of physical interconnects to present the plurality of physical interconnects as a single link to the software.
2. The apparatus of claim 1 , wherein the ATM is an address translation unit (ATU).
3. The apparatus of claim 2 , wherein the ATU is a distributed ATU.
4. The apparatus of claim 2 , wherein each of the plurality of physical interconnects is configured to walk a memory page.
5. The apparatus of claim 1 , wherein the ATM is an address translation cache (ATC).
6. The apparatus of claim 5 , wherein the ATC is a distributed ATC.
7. The apparatus of claim 5 , wherein a respective one of the plurality of physical interconnects is compliant with a protocol, and only the protocol of the respective interconnect associated with the address mapping is allowed to trigger a walk of a memory page.
8. The apparatus of claim 1 , wherein the plurality of physical interconnects are of a single species.
9. The apparatus of claim 8 , wherein the species is a peripheral component interconnect express (PCle) bus.
10. The apparatus of claim 1 , wherein the plurality of physical interconnects are of at least two species.
11. The apparatus of claim 10 , wherein one of the at least two species comprises a bus compatible with a Peripheral Component Interconnect Express (PCle)-based protocol.
12. The apparatus of claim 1 , wherein the accelerator device comprises a plurality of accelerator devices linked to a single address domain.
13. The apparatus of claim 1 , wherein the ATM is further to provide nested GPA to guest virtual address (GVA) translation.
14. An intellectual property (IP) block to provide the apparatus of claim 1 .
15. An accelerator device comprising the apparatus of claim 1 .
16. The accelerator device of claim 15 , wherein the accelerator device comprises a field-programmable gate array (FPGA).
17. The accelerator device of claim 15 , wherein the accelerator device comprises an application-specific integrated circuit (ASIC).
18. The accelerator device of claim 15 , wherein the accelerator device comprises a co-processor.
19. A computing system comprising the accelerator of claim 15 and a host processor, wherein the host processor is to at least partly disable an on-die address translation unit.
20. The computing system of claim 19 , wherein the processor is to fully disable the address translation unit.
21. The computing system of claim 19 , wherein the processor is to disable all but one line of the on-die address translation unit.
22. A computer-implemented method of providing a single address domain to a plurality of interconnects, comprising:
communicatively coupling the plurality of interconnects to an accelerator device and a host device, wherein the host device is to execute software; and
providing an address translation module (ATM) to provide address mapping between host-physical address (HPA) and guest-physical address (GPA) spaces for the accelerator device, wherein the plurality of interconnects share a common GPA domain and wherein address mapping is to be associated with only one of the plurality of interconnects to present the plurality of interconnects as a single link to software.
23. A system comprising:
a first device;
a second device coupled to the first device by a plurality of physical links;
an address translation module (ATM) to provide address mapping between host-physical address (HPA) and guest-physical address (GPA) spaces for the first device, wherein the plurality of devices share a common GPA domain and wherein address mapping is to be associated with only one of the plurality of physical links; and
system software to view the plurality of physical links as a single link coupling the first device to the second device based on the address mapping.
24. The system of claim 23 , wherein the first device comprises an accelerator device.
25. The system of claim 24 , wherein the second device comprises a host processor.
26. The system of claim 23 , wherein the plurality of physical links comprises a first link compliant with a first interconnect protocol and a second link compliant with a different second interconnect protocol.