IP Library Granted Patent US 11,373,585
Granted Patent B2
US 11,373,585 · App. 17/070,338 · Granted Jun 28, 2022

Driving backplane, display panel and method for manufacturing the same

Inventors: Wenqu Liu (Beijing, CN); Qi Yao (Beijing, CN); Feng Zhang (Beijing, CN); Zhijun Lv (Beijing, CN); Liwen Dong (Beijing, CN); Zhao Cui (Beijing, CN); Xiaoxin Song (Beijing, CN); Detian Meng (Beijing, CN); Libo Wang (Beijing, CN)
Assignee: BOE TECHNOLOGY GROUP CO., LTD.
G09G3/32H01L27/156H01L33/387H01L33/62
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Quick Facts
Patent No.
US 11,373,585
App. No.
17/070,338
Granted
Jun 28, 2022
Kind
B2
Abstract

A driving backplane includes a base, and a pixel driving circuit, a first electrode and a first piezoelectric block that are disposed in the sub-pixel region. The pixel driving circuit is disposed on the base. The first electrode is disposed at a side of the pixel driving circuit away from the base. The first electrode includes a first sub-electrode pattern and a second sub-electrode pattern that are in a same layer and are spaced apart to be insulated from each other, and the first sub-electrode pattern is electrically connected to the pixel driving circuit. The first piezoelectric block is disposed between the pixel driving circuit and the first electrode, and the first sub-electrode pattern and the second sub-electrode pattern are in contact with the first piezoelectric block.

Claims (41)

1. A driving backplane, having a sub-pixel region, the driving backplane comprising:

a base;

a pixel driving circuit disposed in the sub-pixel region on the base;

a first electrode disposed in the sub-pixel region and disposed at a side of the pixel driving circuit away from the base; the first electrode including a first sub-electrode pattern and a second sub-electrode pattern that are in a same layer and are spaced apart to be insulated from each other; the first sub-electrode pattern being electrically connected to the pixel driving circuit; and

a first piezoelectric block disposed in the sub-pixel region and between the pixel driving circuit and the first electrode, the first sub-electrode pattern and the second sub-electrode pattern being in contact with the first piezoelectric block.

2. The driving backplane according to claim 1 , wherein the first sub-electrode pattern is disposed around the second sub-electrode pattern in a non-closed manner.

3. The driving backplane according to claim 2 , wherein a shape of the first sub-electrode pattern is a non-closed ring, and the second sub-electrode pattern is disposed within the first sub-electrode pattern.

4. The driving backplane according to claim 2 , wherein a shape of the first sub-electrode pattern is a U-shape, a shape of the second sub-electrode pattern is a bar-shape, and the second sub-electrode pattern is disposed between two opposite sides of the first sub-electrode pattern.

5. The driving backplane according to claim 1 , further comprising:

a second electrode disposed in the sub-pixel region, the second electrode including a third sub-electrode pattern and a fourth sub-electrode pattern that are in a same layer and are spaced apart to be insulated from each other; the third sub-electrode pattern being electrically connected to a first signal line, and the second electrode and the first electrode being disposed in a same layer and insulated from each other; and

a second piezoelectric block disposed in the sub-pixel region, the second piezoelectric block being disposed in a same layer as the first piezoelectric block, and the third sub-electrode pattern and the fourth sub-electrode pattern being in contact with the second piezoelectric block.

6. The driving backplane according to claim 5 , wherein the third sub-electrode pattern is disposed around the fourth sub-electrode pattern in a non-closed manner.

7. The driving backplane according to claim 6 , wherein a shape of the third sub-electrode pattern is a non-closed ring, and the fourth sub-electrode pattern is disposed within the third sub-electrode pattern.

8. The driving backplane according to claim 6 , wherein a shape of the third sub-electrode pattern is a U shape, a shape of the fourth sub-electrode pattern is a bar shape, and the fourth sub-electrode pattern is disposed between two opposite sides of the third sub-electrode pattern.

9. A display panel, comprising:

the driving backplane according to claim 1 ;

a micro light-emitting diode disposed on a side of the first electrode of the driving backplane away from the base, the micro light-emitting diode being disposed in the sub-pixel region; and

a first connecting electrode electrically connecting one of an anode and a cathode of the micro light-emitting diode to the first sub-electrode pattern of the first electrode.

10. The display panel according to claim 9 , wherein the first connecting electrode is disposed on a surface of the first sub-electrode pattern away from the base.

11. The display panel according to claim 10 , wherein the first connecting electrode is made of gold-nickel alloy.

12. The display panel according to claim 9 , wherein the first connecting electrode is disposed on at least one side face of the first sub-electrode pattern.

13. The display panel according to claim 12 , wherein the first sub-electrode pattern is disposed around the second sub-electrode pattern in a non-closed manner; and

the first connecting electrode is disposed on a side face of the first sub-electrode pattern away from the second sub-electrode pattern, or the first connecting electrode is disposed between the first sub-electrode pattern and the second sub-electrode pattern.

14. The display panel according to claim 13 , wherein the first connecting electrode is made of solder paste.

15. The display panel according to claim 9 , wherein the driving backplane further includes:

a second electrode disposed in the sub-pixel region; the second electrode including a third sub-electrode pattern and a fourth sub-electrode pattern that are in a same layer and are spaced apart to be insulated from each other; the third sub-electrode pattern being electrically connected to a first signal line; and the second electrode and the first electrode being disposed in a same layer and insulated from each other; and

a second piezoelectric block disposed in the sub-pixel region; the second piezoelectric block being disposed in a same layer as the first piezoelectric block, and the third sub-electrode pattern and the fourth sub-electrode pattern being in contact with the second piezoelectric block;

the display panel further includes a second connecting electrode disposed in the sub-pixel region; another of the anode and the cathode of the micro light-emitting diode and the third sub-electrode pattern are electrically connected through the second connecting electrode.

16. The display panel according to claim 15 , wherein the micro light-emitting diode further includes a light-emitting functional layer that is in contact with and located at a same side of the anode and the cathode away from the first connecting electrode.

17. The display panel according to claim 16 , wherein the second connecting electrode is disposed on a surface of the third sub-electrode pattern away from the base.

18. The display panel according to claim 16 , wherein the third sub-electrode pattern is disposed around the fourth sub-electrode pattern in a non-closed manner; and

the second connecting electrode is disposed on at least one side face of the third sub-electrode pattern away from the fourth sub-electrode pattern, or; the second connecting electrode is disposed between the third sub-electrode pattern and the fourth sub-electrode pattern.

19. A method for manufacturing the display panel according to claim 9 , comprising:

aligning the micro light-emitting diode with the first electrode of the driving backplane;

applying pressure to the first piezoelectric block in contact with the first sub-electrode pattern and the second sub-electrode pattern, to adsorb the micro light-emitting diode; and

forming the first connecting electrode, to make the one of the anode and the cathode of the micro light-emitting diode and the first sub-electrode pattern of the first electrode be electrically connected through the first connecting electrode.

20. The method according to claim 19 , wherein the driving backplane further includes a second electrode and a second piezoelectric block that are disposed in the sub-pixel region; the second electrode includes a third sub-electrode pattern and a fourth sub-electrode pattern that are in a same layer and are spaced apart to be insulated from each other; the third sub-electrode pattern of the second electrode is electrically connected to a first signal line; and the second electrode and the first electrode disposed in a same sub-pixel region are disposed in a same layer and insulated from each other; the second piezoelectric block is disposed in a same layer as the first piezoelectric block, and the third sub-electrode pattern and the fourth sub-electrode pattern of the second electrode are in contact with the second piezoelectric block; and

the method further includes:

aligning the micro light-emitting diode with the second electrode of the driving backplane while aligning the micro light-emitting diode with the first electrode of the driving backplane;

applying pressure to the second piezoelectric block in contact with the third sub-electrode pattern and the fourth sub-electrode pattern of the second electrode while applying pressure to the first piezoelectric block in contact with the first sub-electrode pattern and the second sub-electrode pattern of the first electrode, to adsorb the micro light-emitting diode; and

forming the second connecting electrode while forming the first connecting electrode, to make another of the anode and the cathode of the micro light-emitting diode and the third sub-electrode pattern of the second electrode be electrically connected through the second connecting electrode.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 14, 2020
From: LIU, WENQU; YAO, QI; ZHANG, FENG; LV, ZHIJUN; DONG, LIWEN; CUI, ZHAO; SONG, XIAOXIN; MENG, DETIAN; WANG, LIBO
To: BOE TECHNOLOGY GROUP CO., LTD.
Reel/Frame 054084/0266 →
Priority Claims (1)
CN 201910979586.3 · Oct 15, 2019 · national
Continuity (1)
Related Publication 20210110761A1 · Apr 15, 2021