IP Library › Granted Patent US 11,373,723
Granted Patent B2
US 11,373,723 · App. 16/278,180 · Granted Jun 28, 2022

Encoder built-in self-test circuit applied in flash memory controller and associated method

Inventor: Tsung-Chieh Yang (Hsinchu, TW)
Assignee: Silicon Motion, Inc.
G11C29/14G06F3/0614G06F3/0658G06F3/0679G11C29/44
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Quick Facts
Patent No.
US 11,373,723
App. No.
16/278,180
Granted
Jun 28, 2022
Kind
B2
Abstract

The present invention provides an encoder built-in self-test (BIST) circuit applied in a flash memory controller, wherein the encoder BIST circuit includes a control circuit and an encoder. In operations of the encoder BIST circuit, without accessing any flash memory, the control circuit generates input data to the encoder, and the encoder encodes the input data to generate a check code to the control circuit, wherein the check code is arranged to determine whether functions of the encoder fail or not.

Claims (34)

1. An encoder built-in self-test (BIST) circuit applied in a flash memory controller, comprising:

a control circuit; and

an encoder;

wherein, without accessing any flash memory, the control circuit generates input data to the encoder, and the encoder encodes the input data to generate a check code to the control circuit, wherein the check code is arranged to determine whether functions of the encoder fail or not;

wherein the control circuit and the encoder perform multiple loop operations, and each of the loop operations comprises:

(a) utilizing the control circuit to generate K th input data to the encoder, wherein K is a positive integer; and

(b) utilizing the encoder to encode the K th input data to generate a K th check code, wherein the K th check code is used by the control circuit to generate (K+1) th input data of the encoder in a next loop operation;

wherein an N th check code generated by the encoder is arranged to determine whether the functions of the encoder fail or not, wherein N is a predetermined value equal to or greater than three.

2. The encoder BIST circuit of claim 1 , wherein the control circuit comprises:

a random data generation circuit, arranged to generate the (K+1) th input data to the encoder; and

a seed data generation circuit, coupled to the random data generation circuit, arranged to generate seed data to the random data generation circuit according to a (K+1) th check code, to allow the random data generation circuit to generate (K+2) th input data.

3. The encoder BIST circuit of claim 2 , wherein the seed data generation circuit performs a cyclic redundancy check (CRC) operation on the K th check code to generate the seed data.

4. The encoder BIST circuit of claim 2 , wherein the control circuit further comprises:

a multiplexer, arranged to selectively transmit predetermined input data or the (K+1) th input data generated by the random data generation circuit to the encoder, wherein the predetermined input data is first data generated by the control circuit to the encoder.

5. An encoder built-in self-test (BIST) method applied in a flash memory controller, comprising:

without accessing any flash memory:

generating input data to an encoder;

utilizing the encoder to encode the input data to generate a check code; and

determining whether functions of the encoder fail or not according to the check code;

wherein the operation of generating the input data is performed by a control circuit, the control circuit and the encoder perform multiple loop operations, and each of the loop operations comprises:

(a) utilizing the control circuit to generate a K th input data to the encoder,

wherein K is a positive integer; and

(b) utilizing the encoder to encode the K th input data to generate a K th check code, wherein the K th check code is used by the control circuit to generate (K+1) th input data of the encoder in a next loop operation;

wherein an N th check code generated by the encoder is arranged to determine whether the functions of the encoder fail or not, wherein N is a predetermined value equal to or greater than three.

6. The encoder BIST method of claim 5 , wherein the step of generating the input data to the encoder comprises:

activating a control circuit to generate the input data to the encoder after receiving a self-test enable signal from outside of the flash memory controller.

7. The encoder BIST method of claim 6 , wherein the self-test enable signal is inputted from a pad or a pin of the flash memory controller.

8. The encoder BIST method of claim 7 , wherein the self-test enable signal is inputted during a chip probe (CP) phase within a wafer level test, or inputted during a final test (FT) phase within a package level test.

9. The encoder BIST method of claim 5 , wherein the step of determining whether the functions of the encoder fail or not according to the check code comprises:

determining whether the check code or seed data generated by compressing the check code matches predetermined data, to determine whether the functions of the encoder fail or not.

10. The encoder BIST method of claim 5 , wherein the step of determining whether the functions of the encoder fail or not according to the check code comprises:

transmitting the check code or seed data generated by compressing the check code to another device through a pad or a pin of the flash memory controller, to allow said other device to determine whether the check code or the seed data matches predetermined data, to determine whether the functions of the encoder fail or not.

11. The encoder BIST method of claim 5 , wherein each of the loop operations further comprises:

generating seed data to the control circuit according to the K th check code, to allow the control circuit to generate (K+1) th input data.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 18, 2019
From: YANG, TSUNG-CHIEH
To: SILICON MOTION INC.
Reel/Frame 048358/0417 →
Priority Claims (1)
TW 107135926 · Oct 12, 2018 · national
Continuity (1)
Related Publication 20200118641A1 · Apr 16, 2020
Cited By (1)
US 12,205,617