Complementary logic circuit and application to thin-film hybrid electronics
View Patent ↗A complementary circuit, including a logic unit which includes pull-up depletion-mode MOS transistors and pull-down depletion-mode MOS transistors and a level shifting circuit coupled to the logic unit.
1. A complementary circuit, comprising:
a logic unit configured to provide a logic function and a digital operation, the logic unit comprising pull-up depletion-mode circuit MOS transistors and pull-down depletion-mode MOS transistors, the logic unit including a digital switch; and
a level shifting circuit including diodes which are implemented by a circuitry arrangement of a heterojunction field-effect transistor (HJFET) device,
wherein an input and an output of the level shifting circuit comprise complementary signals,
wherein the depletion-mode MOS devices and the HJFET devices are monolithically integrated,
wherein the logic unit and the level shifting circuit comprise a first capacitor and a second capacitor which are implemented by a circuitry arrangement of the depletion-mode MOS transistors, and
wherein, the level shifter operates in a first phase and a second phase such that:
in the first phase:
the first capacitor is charged to a first value while the second capacitor is discharged; and
in the second phase:
the first capacitor is connected to the second capacitor and by preservation of charge, the second capacitor is charged to a predetermined value.
2. The complementary circuit of claim 1 , wherein input signals applied to gates of the pull-up depletion-mode MOS transistors are complementary to input signals applied to gates of the pull-down depletion-mode MOS transistors.
3. The complementary circuit of claim 1 , wherein the level shifting circuit comprises depletion-mode MOS transistors having a single channel conductivity type and at least one diode.
4. The complementary circuit of claim 1 , wherein the level shifting circuit shifts an output voltage range of the logic unit to a same range as an input voltage range of the logic unit.
5. The complementary circuit of claim 1 , wherein the level shifting circuit comprises diodes which are implemented by a circuitry arrangement of heterojunction field-effect transistor (HJFET) devices.
6. The complementary circuit of claim 1 , wherein the level shifting circuit is coupled to the logic unit.
7. The complementary circuit of claim 1 , wherein the pull-up and pull-down transistors include a single channel conductivity type including negative threshold voltages.
8. The complementary circuit of claim 1 , wherein the pull-up and pull-down transistors are both n-channel or are both p-channel.
9. The complementary circuit of claim 1 , wherein, in the first phase, V X is a first value and V x is a second value less than the first value, and
wherein, in the second phase, the second value of V x is greater than the first value of V X .
10. A system, comprising:
a circuit comprising a heterojunction field-effect transistor (HJFET) device and a depletion-mode MOS device; and
a complementary circuit coupled to the circuit, the complementary circuit including:
a logic unit configured to provide a logic function and a digital operation, the logic unit comprising pull-up depletion-mode MOS transistors and pull-down depletion-mode MOS transistors, the logic unit including a digital switch; and
a level shifting circuit including diodes which are implemented by a circuitry arrangement of the heterojunction field-effect transistor (HJFET) device,
wherein an input and an output of the level shifting circuit comprise complementary signals,
wherein the depletion-mode MOS devices and the HJFET devices are monolithically integrated,
wherein the logic unit and the level shifting circuit comprise a first capacitor and a second capacitor which are implemented by a circuitry arrangement of the depletion-mode MOS transistors, and
wherein, the level shifter operates in a first phase and a second phase such that:
in the first phase:
the first capacitor is charged to a first value while the second capacitor is discharged; and
in the second phase:
the first capacitor is connected to the second capacitor and by preservation of charge, the second capacitor is charged to a predetermined value.
11. The system of claim 10 , wherein input signals applied to gates of the pull-up depletion-mode MOS transistors are complementary to input signals applied to gates of the pull-down depletion-mode MOS transistors.
12. The system of claim 10 , wherein the level shifting circuit comprises depletion-mode MOS transistors having a single channel conductivity type and at least one diode.
13. The system of claim 10 , wherein the level shifting circuit shifts an output voltage range of the logic unit to approximately a same range as an input voltage range of the logic unit.
14. The system of claim 10 , wherein the level shifting circuit comprises diodes which are implemented by a circuitry arrangement of heterojunction field-effect transistor (HJFET) devices.
15. The system of claim 10 , wherein the level shifting circuit shifts an output voltage range of the logic unit to a same range as an input voltage range of the logic unit.
16. The system of claim 10 , wherein the level shifting circuit is coupled to the logic unit.
17. An active matrix display, comprising:
a row driver implemented using a complementary circuit, the complementary circuit including:
a logic unit configured to provide a logic function and a digital operation, the logic unit comprising pull-up depletion-mode MOS transistors and pull-down depletion-mode MOS transistors, the logic unit including a digital switch; and
a level shifting circuit including diodes which are implemented by a circuitry arrangement of a heterojunction field-effect transistor (HJFET) device,
wherein an input and an output of the level shifting circuit comprise complementary signals,
wherein the depletion-mode MOS devices and the HJFET devices are monolithically integrated,
wherein the logic unit and the level shifting circuit comprise a first capacitor and a second capacitor which are implemented by a circuitry arrangement of the depletion-mode MOS transistors, and
wherein, the level shifter operates in a first phase and a second phase such that:
in the first phase:
the first capacitor is charged to a first value while the second capacitor is discharged; and
in the second phase:
the first capacitor is connected to the second capacitor and by preservation of charge, the second capacitor is charged to a predetermined value.