Selective capping processes and structures formed thereby
Embodiments disclosed herein relate generally to capping processes and structures formed thereby. In an embodiment, a conductive feature, formed in a dielectric layer, has a metallic surface, and the dielectric layer has a dielectric surface. The dielectric surface is modified to be hydrophobic by performing a surface modification treatment. After modifying the dielectric surface, a capping layer is formed on the metallic surface by performing a selective deposition process. In another embodiment, a surface of a gate structure is exposed through a dielectric layer. A capping layer is formed on the surface of the gate structure by performing a selective deposition process.
1. A method of manufacturing a semiconductor device, the method comprising:
forming a gate structure embedded within a dielectric layer over a semiconductor fin;
selectively reacting a reactant with the dielectric layer to form a monolayer of a hydrophobic material; and
selectively depositing tungsten onto the gate structure, the tungsten having a chlorine concentration of less than about 1%.
2. The method of claim 1 , wherein the reactant comprises tetramethylsilane (Si(CH 3 ) 4 ).
3. The method of claim 1 , wherein the reactant comprises N,N-dimethyltrimethylsilylamine ((CH 3 ) 2 —N—Si—(CH 3 ) 3 ).
4. The method of claim 1 , wherein the reactant comprises a silane derivative.
5. The method of claim 1 , wherein the selectively reacting the reactant comprises a wet process.
6. The method of claim 1 , wherein the selectively reacting the reactant comprises a dry process.
7. The method of claim 1 , further comprising recessing the gate structure prior to the selectively reacting the reactant with the dielectric layer.
8. A method of manufacturing a semiconductor device, the method comprising:
depositing a dielectric layer over a source/drain region;
forming a gate structure planar with the dielectric layer;
exposing the dielectric layer to a silane derivative with one or more hydrophobic functional groups;
exposing the gate structure to fluorine-free tungsten precursors; and
depositing a second dielectric layer over a product of the fluorine-free tungsten precursors.
9. The method of claim 8 , wherein the exposing the gate structure to the fluorine-free tungsten precursors forms a tungsten material with a chlorine concentration of less than 1%.
10. The method of claim 8 , wherein the exposing the dielectric layer comprises a wet process.
11. The method of claim 10 , wherein the wet process immerses the dielectric layer to a bath comprising the silane derivative.
12. The method of claim 11 , wherein the bath has a temperature of between about 20° C. and about 80° C.
13. The method of claim 12 , wherein the bath is a mixture of the silane derivative, isopropyl alcohol, and deionized water.
14. The method of claim 8 , recessing the gate structure after the forming the gate structure planar with the dielectric layer.
15. A method of manufacturing a semiconductor device, the method comprising:
forming a first conductive contact through a first dielectric layer to make physical contact with a capping layer and to make electrical contact with a gate structure, wherein there is less than 1% of chlorine within the capping layer; and
forming a second conductive contact through the first dielectric layer, a second dielectric layer, and a monolayer between the first dielectric layer and the second dielectric layer to make electrical contact with a source/drain region adjacent to the gate structure, the monolayer comprising hydrophobic functional groups.
16. The method of claim 15 , wherein the hydrophobic functional groups comprises a hydrocarbon.
17. The method of claim 16 , wherein the hydrophobic functional groups have a general form of —C X H 2X+1 .
18. The method of claim 15 , wherein the capping layer has a thickness in a range from 30 Å to 50 Å.
19. The method of claim 15 , wherein the capping layer has a concentration of chlorine that is less than 1%.
20. The method of claim 15 , wherein the capping layer has a bottom surface that shares a plane with a top surface of the second dielectric layer.