Metamorphic high electron mobility transistor-heterojunction bipolar transistor integration
A semiconductor device having metamorphic high electron mobility transistor (HEMT)-heterojunction bipolar transistor (HBT) integration on a semiconductor substrate. An example semiconductor device generally includes a semiconductor substrate, a bipolar junction transistor (BJT) disposed above the semiconductor substrate and comprising indium, and a HEMT disposed above the semiconductor substrate and comprising indium.
1. A semiconductor device, comprising:
a semiconductor substrate, wherein the semiconductor substrate comprises silicon;
a bipolar junction transistor (BJT) disposed above the semiconductor substrate and comprising indium phosphide; and
a high electron mobility transistor (HEMT) disposed above the semiconductor substrate and comprising indium.
2. The semiconductor device of claim 1 , wherein the BJT is a heterojunction bipolar transistor (HBT).
3. The semiconductor device of claim 2 , wherein the HBT further comprises:
a collector layer comprising indium phosphide;
an emitter layer comprising indium phosphide; and
a base layer comprising indium gallium arsenide.
4. The semiconductor device of claim 3 , wherein:
the collector layer is disposed above the semiconductor substrate;
the base layer is disposed above the collector layer; and
the emitter layer is disposed above the base layer.
5. The semiconductor device of claim 4 , wherein the HBT further comprises a sub-collector layer disposed below the collector layer and comprising indium gallium arsenide.
6. The semiconductor device of claim 5 , wherein:
the sub-collector layer has an indium composition of 30% to 53%; and
the base layer has an indium composition of 30% to 53%.
7. The semiconductor device of claim 1 , wherein the HEMT is a metamorphic HEMT.
8. The semiconductor device of claim 1 , wherein the HEMT further comprises:
a buffer layer disposed above the semiconductor substrate; and
a channel layer disposed above the buffer layer.
9. The semiconductor device of claim 8 , wherein the HEMT further comprises:
a barrier layer disposed above the channel layer; and
a cap layer disposed above the barrier layer.
10. The semiconductor device of claim 9 , wherein:
the buffer layer comprises indium aluminum arsenide;
the channel layer comprises indium gallium arsenide;
the barrier layer comprises indium aluminum arsenide; and
the cap layer comprises indium gallium arsenide.
11. The semiconductor device of claim 10 , wherein:
the buffer layer comprises indium aluminum arsenide having a chemical formula of In x Al 1-x As;
x is within a range of 0.1 to 0.53;
the channel layer has an indium composition of 30% to 53%; and
the barrier layer has an indium composition of 30% to 53%.
12. The semiconductor device of claim 9 , further comprising:
an isolation region disposed between the BJT and the HEMT; and
a semiconductor layer disposed between the semiconductor substrate and the buffer layer, wherein the BJT is disposed above the cap layer.
13. A radio frequency front-end (RFFE) integrated circuit (IC) comprising the semiconductor device of claim 1 , wherein a power amplifier of the RFFE IC includes the BJT, and wherein a low noise amplifier of the RFFE IC includes the HEMT.
14. A method of fabricating a semiconductor device, comprising:
forming a semiconductor stack structure above a semiconductor substrate, wherein the semiconductor substrate comprises silicon and wherein the semiconductor stack structure comprises indium;
forming a bipolar junction transistor (BJT) above the semiconductor stack structure, wherein the BJT comprises indium phosphide; and
forming a high electron mobility transistor (HEMT) from the semiconductor stack structure.
15. The method of claim 14 , wherein the forming the semiconductor stack structure comprises forming a buffer layer, a channel layer, a barrier layer, and a cap layer above the semiconductor substrate.
16. The method of claim 15 , wherein:
the buffer layer is formed above the semiconductor substrate and comprises indium aluminum arsenide;
the channel layer is formed above the buffer layer and comprises indium gallium arsenide;
the barrier layer is formed above the channel layer and comprises indium aluminum arsenide; and
the cap layer is formed above the barrier layer and comprises indium gallium arsenide.
17. The method of claim 15 , wherein the forming the BJT comprises forming a collector layer, a base layer, and an emitter layer above the semiconductor stack structure.
18. The method of claim 15 , wherein:
the BJT comprises a collector layer, a base layer, and an emitter layer;
the collector layer is formed above the semiconductor stack structure and comprises indium phosphide;
the base layer is formed above the collector layer and comprises indium gallium arsenide; and
the emitter layer is formed above the base layer and comprises indium phosphide.
19. The method of claim 15 , further comprising forming an isolation region intersecting the semiconductor stack structure and between the BJT and the HEMT.
20. A semiconductor device comprising:
a semiconductor substrate;
a bipolar junction transistor (BJT) disposed above the semiconductor substrate and comprising indium phosphide; and
a high electron mobility transistor (HEMT) disposed above the semiconductor substrate and comprising indium, wherein the BJT is a heterojunction bipolar transistor (HBT) and wherein the HBT further comprises:
a collector layer disposed above the semiconductor substrate and comprising indium phosphide;
a base layer disposed above the collector layer and comprising indium gallium arsenide; and
an emitter layer disposed above the base layer and comprising indium phosphide.