IP Library › Granted Patent US 11,380,772
Granted Patent B2
US 11,380,772 · App. 17/012,832 · Granted Jul 5, 2022

Gate structure and patterning method for multiple threshold voltages

Inventors: Chung-Liang Cheng (Changhua County, TW); Ziwei Fang (Hsinchu, TW)
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
H01L29/4966H01L21/823821H01L27/0886H01L27/0924H01L29/66545H01L29/7853
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Quick Facts
Patent No.
US 11,380,772
App. No.
17/012,832
Granted
Jul 5, 2022
Kind
B2
Abstract

A semiconductor device and a method of forming the same are provided. In one embodiment, the semiconductor device includes a semiconductor substrate, a plurality of channel regions including first, second, and third p-type channel regions as well as first, second, and third n-type channel regions, and a plurality of gate structures. The plurality of gate structures includes an interfacial layer (IL) disposed over the plurality of channel regions, a first high-k (HK) dielectric layer disposed over the first p-type channel region and the first n-type channel region, a second high-k dielectric layer disposed over the first n-type channel region, the second n-type channel region, the first p-type channel region, and the second p-type channel region; and a third high-k dielectric layer disposed over the plurality of channel regions. The first, second and third high-k dielectric layers are different from one another.

Claims (92)

1. A method, comprising:

providing a workpiece including a semiconductor substrate, a plurality of fins disposed over the semiconductor substrate, the plurality of fins comprising a plurality of channel regions including first, second, and third p-type channel regions as well as first, second, and third n-type channel regions; and

forming a plurality of gate structures over the plurality of channel regions, comprising:

forming an interfacial layer over the plurality of channel regions,

selectively forming a first high-k dielectric layer over the interfacial layer over the first n-type channel region and the first p-type channel region,

selectively forming a second high-k dielectric layer over the interfacial layer over the second n-type channel region and the second p-type channel region, and over the first high-k dielectric layer over the first n-type channel region and the first p-type channel region,

forming a third high-k dielectric layer over the second high-k dielectric layer disposed over the first n-type channel region, the first p-type channel region, the second n-type channel region, the second p-type channel region, and over the interfacial layer disposed over the third n-type channel region and the third p-type channel region,

selectively forming a p-type work function layer over the first, second and third p-type channel regions,

forming an n-type work function layer over the plurality of channel regions, and

forming a fill metal layer over the plurality of channel regions,

wherein the first, second and third high-k dielectric layers are different from one another.

2. The method of claim 1 , wherein the selectively forming of the first high-k dielectric layer comprises:

depositing the first high-k dielectric layer over the plurality of channel regions;

depositing a metal nitride hard mask over the first high-k dielectric layer;

patterning the metal nitride hard mask by removing the metal nitride hard mask over the second n-type channel region, the third n-type channel region, the second p-type channel region, and the third p-type channel region; and

recessing the deposited first high-k dielectric layer using the patterned metal nitride hard mask layer as an etch mask.

3. The method of claim 2 , wherein the metal nitride hard mask comprises titanium, tantalum, or tungsten.

4. The method of claim 1 , further comprising:

before the selectively forming of the p-type work function layer, depositing a capping layer over the third high-k dielectric layer over the plurality of channel regions; and

depositing a barrier layer over the capping layer over the plurality of channel regions.

5. The method of claim 1 ,

wherein the selectively forming of the first high-k dielectric layer comprises forming the first high-k dielectric layer to a first thickness,

wherein the selectively forming of the second high-k dielectric layer comprises forming the second high-k dielectric layer to a second thickness,

wherein the selectively forming the third high-k dielectric layer comprises forming the third high-k dielectric layer to a third thickness,

wherein the third thickness is greater than the second thickness and the second thickness is greater than the first thickness.

6. The method of claim 5 ,

wherein the first thickness is between about 5 Å and 10 Å,

wherein the second thickness is between about 10 Å and 15 Å,

wherein the third thickness is between about 15 Å and 20 Å.

7. The method of claim 1 , wherein the first high-k dielectric layer, the second high-k dielectric layer, and the third high-k dielectric layer comprise HfO 2 , Al 2 O 3 , TiO 2 , La 2 O 3 , HfSiO 4 , ZrO 2 , Y 2 O 3 , or SrTiO 3 .

8. A method, comprising:

providing a workpiece comprising a first, a second, and a third n-type channel regions;

forming an interfacial layer over the first, second, and third n-type channel regions;

after the forming of the interfacial layer, selectively forming a first high-k dielectric layer over the interfacial layer over the first n-type channel region, the selectively forming of the first high-k dielectric layer comprising:

depositing the first high-k dielectric layer over the first n-type channel region, the second n-type channel region, and the third n-type channel region, and

selectively removing the first high-k dielectric layer over the second n-type channel region and the third n-type channel region;

after the selectively removing of the first high-k dielectric layer, selectively forming a second high-k dielectric layer over the interfacial layer disposed over the second n-type channel region and over the first high-k dielectric layer disposed over the first n-type channel region;

depositing a third high-k dielectric layer over the second high-k dielectric layer disposed over the first n-type channel region and the second n-type channel region, and over the interfacial layer disposed over the third n-type channel region;

forming an n-type work function layer over the third high-k dielectric layer disposed over the first, second, and third n-type channel regions; and

forming a fill metal layer over the n-type work function layer,

wherein the first, second and third high-k dielectric layers are different from one another.

9. The method of claim 8 ,

wherein the first high-k dielectric layer is doped with aluminum,

wherein the second high-k dielectric layer is not doped,

wherein the third high-k dielectric layer is doped with lanthanum.

10. The method of claim 8 ,

wherein the selectively forming of the first high-k dielectric layer comprises forming the first high-k dielectric layer to a first thickness,

wherein the selectively forming of the second high-k dielectric layer comprises forming the second high-k dielectric layer to a second thickness,

wherein the selectively forming the third high-k dielectric layer comprises forming the third high-k dielectric layer to a third thickness,

wherein the third thickness is greater than the second thickness and the second thickness is greater than the first thickness.

11. The method of claim 10 ,

wherein the first thickness is between about 5 Å and 10 Å,

wherein the second thickness is between about 10 Å and 15 Å,

wherein the third thickness is between about 15 Å and 20 Å.

12. The method of claim 8 , further comprising:

before the forming of the n-type work function layer, depositing a capping layer over the third high-k dielectric layer over the first, second, and third n-type channel regions; and

depositing a barrier layer over the capping layer disposed over the first, second, and third n-type channel regions.

13. The method of claim 8 , further comprising:

before the forming of the n-type work function layer, depositing a p-type work function layer over the workpiece; and

selectively removing the p-type work function layer over the first, second, and third n-type channel regions.

14. The method of claim 8 , further comprising:

before the forming of the fill metal layer, depositing a glue layer over the n-type work function layer disposed over the first, second, and third n-type channel regions.

15. The method of claim 14 , wherein the glue layer comprises titanium nitride.

16. A method, comprising:

providing a workpiece comprising a first, a second, and a third p-type channel regions;

forming an interfacial layer over the first, second, and third p-type channel regions;

after the forming of the interfacial layer, selectively forming a first high-k dielectric layer over the interfacial layer over the first p-type channel region, the selectively forming of the first high-k dielectric layer comprising:

depositing the first high-k dielectric layer over the first p-type channel region, the second p-type channel region, and the third p-type channel region, and

selectively removing the first high-k dielectric layer over the second p-type channel region and the third p-type channel region;

after the selectively removing of the first high-k dielectric layer, selectively forming a second high-k dielectric layer over the interfacial layer disposed over the second p-type channel region and over the first high-k dielectric layer disposed over the first p-type channel region;

depositing a third high-k dielectric layer over the second high-k dielectric layer disposed over the first p-type channel region and the second p-type channel region, and over the interfacial layer disposed over the third p-type channel region;

forming a p-type work function layer over the third high-k dielectric layer disposed over the first, second, and third p-type channel regions;

forming an n-type work function layer over the p-type work function layer; and

forming a fill metal layer over the n-type work function layer,

wherein the first, second and third high-k dielectric layers are different from one another.

17. The method of claim 16 ,

wherein the first high-k dielectric layer is doped with aluminum,

wherein the second high-k dielectric layer is not doped,

wherein the third high-k dielectric layer is doped with lanthanum.

18. The method of claim 16 ,

wherein the selectively forming of the first high-k dielectric layer comprises forming the first high-k dielectric layer to a first thickness,

wherein the selectively forming of the second high-k dielectric layer comprises forming the second high-k dielectric layer to a second thickness,

wherein the selectively forming the third high-k dielectric layer comprises forming the third high-k dielectric layer to a third thickness,

wherein the third thickness is greater than the second thickness and the second thickness is greater than the first thickness.

19. The method of claim 16 , further comprising:

before the forming of the p-type work function layer, depositing a capping layer over the third high-k dielectric layer over the first, second, and third p-type channel regions; and

depositing a barrier layer over the capping layer disposed over the first, second, and third p-type channel regions,

wherein the capping layer comprises titanium, nitrogen, or silicon,

wherein the barrier layer comprises tantalum nitride.

20. The method of claim 16 , further comprising:

before the forming of the fill metal layer, depositing a glue layer over the n-type work function layer disposed over the first, second, and third p-type channel regions,

wherein the glue layer comprises titanium nitride.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 4, 2020
From: CHENG, CHUNG-LIANG; FANG, ZIWEI
To: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Reel/Frame 053709/0679 →
Continuity (3)
Division 16363109 · Mar 25, 2019
Provisional Application 62749883 · Oct 24, 2018
Related Publication 20200403078A1 · Dec 24, 2020