Field-effect transistor device with gate spacer structure
Semiconductor devices and methods of forming the same are provided. A method according to the present disclosure includes forming a semiconductor element over a substrate, the semiconductor element including a channel region and a source/drain region, forming a dummy gate stack over the channel region of the semiconductor element, depositing a first spacer layer over sidewalls of the dummy gate stack, depositing a second spacer layer over the first spacer layer, wherein the second spacer layer includes at least one silicon sublayer and at least one nitrogen-containing sublayer, after the depositing of the second spacer layer, etching the source/drain region of the semiconductor element to form a source/drain recess, and after the etching, removing the second spacer layer.
1. A method, comprising:
forming a semiconductor element over a substrate, the semiconductor element including a channel region and a source/drain region;
forming a dummy gate stack over the channel region of the semiconductor element;
depositing a first spacer layer over sidewalls of the dummy gate stack;
depositing a second spacer layer over the first spacer layer, wherein the second spacer layer comprises at least one silicon sublayer and at least one nitrogen-containing sublayer;
after the depositing of the second spacer layer, etching the source/drain region of the semiconductor element to form a source/drain recess; and
after the etching, removing the second spacer layer.
2. The method of claim 1 , wherein a dielectric constant of the first spacer layer is smaller than a dielectric constant of the at least one silicon sublayer and a dielectric constant of the at least one nitrogen-containing sublayer.
3. The method of claim 1 , wherein the depositing of the second spacer layer comprises:
depositing the at least one silicon sublayer using dichlorosilane (DCS) at a deposition temperature between about 500° C. and about 600° C.
4. The method of claim 1 , wherein the depositing of the second spacer layer comprises:
depositing the at least one silicon sublayer using monochlorosilane (MCS) at a deposition temperature between about 350° C. and about 450° C.
5. The method of claim 1 , wherein the depositing of the second spacer layer comprises:
depositing the at least one silicon sublayer using hexachlorodisilane (HCD) at a deposition temperature between about 540° C. and about 640° C.
6. The method of claim 1 , wherein the etching of the source/drain region of the semiconductor element comprises use of oxygen and a fluorocarbon.
7. The method of claim 6 , wherein the etching of the source/drain region of the semiconductor element produces a polymeric byproduct that includes silicon, carbon, oxygen, and fluorine.
8. The method of claim 1 , wherein the removing of the second spacer layer comprises use of hot phosphoric acid solution.
9. A method, comprising:
providing a workpiece that includes:
a semiconductor element comprising a channel region and a source/drain region, and
a dummy gate stack wrapping over the channel region of the semiconductor element;
depositing a first spacer layer over sidewalls of the dummy gate stack;
depositing a second spacer layer over the first spacer layer, wherein the second spacer layer comprises at least one silicon sublayer and at least one nitrogen-containing sublayer;
after the depositing of the second spacer layer, etching the source/drain region of the semiconductor element to form a source/drain recess;
after the etching, removing the second spacer layer; and
after the removing of the second spacer layer, forming a source/drain feature in the source/drain recess.
10. The method of claim 9 , wherein a thickness of each of the at least one silicon sublayer is between about 0.1 Å and about 20 Å.
11. The method of claim 9 , wherein the depositing of the second spacer layer comprises:
depositing one of the at least one silicon sublayer directly on the first spacer layer.
12. The method of claim 9 , wherein the depositing of the second spacer layer comprises:
depositing the at least one silicon sublayer using atomic layer deposition (ALD).
13. The method of claim 9 , wherein the depositing of the at least one silicon sublayer comprises a deposition pressure between about 1 Torr and about 10 Torr.
14. The method of claim 9 , wherein the at least one nitrogen-containing sublayer comprises silicon carbonitride, silicon boron nitride, silicon nitride, silicon oxycarbonitride, or silicon oxynitride.
15. A method, comprising:
forming a dummy gate stack over a semiconductor element;
depositing a first spacer layer over sidewalls of the dummy gate stack; and
depositing a second spacer layer over the first spacer layer, wherein the depositing of the second spacer layer comprises:
depositing a silicon sublayer over the first spacer layer using atomic layer deposition (ALD), and
depositing a nitrogen-containing sublayer over the silicon sublayer using ALD.
16. The method of claim 15 , wherein the depositing of the silicon sublayer comprises:
use of dichlorosilane (DCS), and
a deposition temperature between about 500° C. and about 600° C.
17. The method of claim 15 , wherein the depositing of the silicon sublayer comprises:
use of monochlorosilane (MCS), and
a deposition temperature between about 350° C. and about 450° C.
18. The method of claim 15 , wherein the depositing of the silicon sublayer comprises:
use of hexachlorodisilane (HCD), and
a deposition temperature between about 540° C. and about 640° C.
19. The method of claim 15 , wherein the nitrogen-containing sublayer comprises silicon carbonitride, silicon boron nitride, silicon nitride, silicon oxycarbonitride, or silicon oxynitride.
20. The method of claim 15 , wherein the depositing of the second spacer layer further comprises:
depositing another nitrogen-containing sublayer over the silicon sublayer, and
depositing another silicon sublayer over the another nitrogen-containing sublayer,
wherein the nitrogen-containing sublayer is deposited on the another silicon sublayer.