IP Library › Granted Patent US 11,380,840
Granted Patent B2
US 11,380,840 · App. 16/824,862 · Granted Jul 5, 2022

Memory cell with magnetic access selector apparatus

Inventor: Mauricio Manfrini (Zhubei, TW)
Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
H01L43/08H01L27/222H01L43/02
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Quick Facts
Patent No.
US 11,380,840
App. No.
16/824,862
Granted
Jul 5, 2022
Kind
B2
Abstract

An integrated chip has a memory cell that includes a magnetic tunnel junction (MTJ) device and an access selector apparatus. The MTJ device includes a free layer and a pinned layer. The access selector apparatus includes a first metal structure and a second metal structure separated by one or more non-metallic layers. The first metal structure includes a polarized magnetic layer. The polarized magnetic layer produces a magnetic field that extends through the free layer, tilting its magnetic field and thereby substantially reducing a switching time for the MTJ device. The access selector apparatus may be a bipolar selector. The polarized magnetic layer may be incorporated into an electrode of the bipolar selector. Both the access selector apparatus and the MTJ device may be formed by a stack of material layers. The resulting memory cell may be compact and have good write speed.

Claims (41)

1. An integrated chip, comprising:

a magnetic tunnel junction (MTJ) device having a first electrode and a second electrode; and

a bipolar selector for the MTJ device, the bipolar selector comprising a first metal structure and a second metal structure separated by one or more non-metallic layers, the one or more non-metallic layers comprising two insulators having different band gap energies;

wherein one of the first metal structure and the second metal structure is coupled to the second electrode; and

the first metal structure is an electrode for the bipolar selector and comprises a polarized ferromagnetic layer.

2. The integrated chip of claim 1 , wherein one of the two insulators is an oxide of a metal of the polarized ferromagnetic layer.

3. The integrated chip of claim 1 , wherein the MTJ device and the bipolar selector are formed by a stack of material layers.

4. The integrated chip of claim 3 , wherein the polarized ferromagnetic layer has in-plane polarization.

5. The integrated chip of claim 4 , wherein the MTJ device comprises a pinned layer having perpendicular magnetic polarization.

6. The integrated chip of claim 1 , wherein the first metal structure comprises an electrode layer distinct from the polarized ferromagnetic layer.

7. The integrated chip of claim 1 , wherein the polarized ferromagnetic layer alters a direction of polarization of a free layer of the MTJ device so as to reduce a switching time of the MTJ device.

8. The integrated chip of claim 1 , wherein the bipolar selector is effective to reduce leak currents through the MTJ device when the MTJ device is not selected for a read, write, or erase operation.

9. The integrated chip of claim 1 , wherein the bipolar selector is directly over or directly under the MTJ device.

10. An integrated chip comprising:

a magnetic tunnel junction (MTJ) device having a first electrode and a second electrode; and

an access selector apparatus for the MTJ device comprising a first metal structure and a second metal structure separated by one or more non-metallic layers;

wherein one of the first metal structure and the second metal structure is coupled to the second electrode;

the first metal structure comprises a polarized ferromagnetic layer;

the first metal structure is an electrode for the access selector apparatus;

the access selector apparatus is a bipolar selector;

the MTJ device and the access selector apparatus are formed by a stack of material layers;

the polarized ferromagnetic layer has in-plane polarization; and

the MTJ device comprises a pinned layer having perpendicular magnetic polarization.

11. The integrated chip of claim 10 , wherein the first metal structure and the second metal structure are separated by two insulators having different band gap energies.

12. The integrated chip of claim 11 , wherein one of the two insulators is an oxide of the polarized ferromagnetic layer.

13. The integrated chip of claim 10 , wherein the access selector apparatus is effective to reduce leak currents through the MTJ device during read, write, and erase operations for which the MTJ device is not selected.

14. The integrated chip of claim 10 , wherein the polarized ferromagnetic layer is operative to reduce a switching time of the MTJ device.

15. The integrated chip of claim 10 , wherein the bipolar selector is directly over or directly under the MTJ device.

16. An integrated chip, comprising:

a magnetic tunnel junction (MTJ) device disposed within a dielectric structure over a substrate, the MTJ device comprising an MTJ disposed between a first MTJ electrode and a second MTJ electrode; and

a bipolar selector comprising a middle structure disposed between a first bipolar selector electrode and a second bipolar selector electrode;

wherein the MTJ comprises a pinned layer having perpendicular magnetization;

the second bipolar selector electrode is coupled to or integral with the first MTJ electrode;

the middle structure is one or more layers of insulators and/or semiconductors; and

one of the first bipolar selector electrode and the second bipolar selector electrode comprises a polarized magnetic layer having in-plane polarization.

17. The integrated chip of claim 16 , wherein the first bipolar selector electrode comprises the polarized magnetic layer.

18. The integrated chip of claim 16 , wherein:

the MTJ device comprises a free layer; and

the polarized magnetic layer has a magnetic field that is effective to reduce a number of precession cycles undergone by the free layer during switching of the MTJ device.

19. The integrated chip of claim 16 , wherein the middle structure comprises two insulators having different band gap energies.

20. The integrated chip of claim 19 , wherein one of the two insulators is an oxide of the polarized magnetic layer.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 14, 2020
From: MANFRINI, MAURICIO
To: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Reel/Frame 052386/0183 →
Continuity (1)
Related Publication 20210296573A1 · Sep 23, 2021
Cited By (1)
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