IP Library › Granted Patent US 11,385,998
Granted Patent B2
US 11,385,998 · App. 16/700,806 · Granted Jul 12, 2022

Memory system, data processing system and operation method of the same

Inventor: Jong-Min Lee (Seoul, KR)
Assignee: SK hynix Inc.
G06F12/0246G06F11/076G06F11/102G06F11/3037G06F12/0882G11C16/3418
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Quick Facts
Patent No.
US 11,385,998
App. No.
16/700,806
Granted
Jul 12, 2022
Kind
B2
Abstract

A memory system includes a memory device including a memory device including a plurality of blocks, each block having a plurality of pages to store data; and a controller suitable for selecting specific memory blocks among the plurality memory blocks, acquiring error bit information of the plurality of pages in each of the specific memory blocks, generating a memory block group management list of each of the specific memory blocks to classify the specific memory blocks into different memory block groups or a same memory block group based on the error bit information, and performing a test read operation on the plurality of pages in each of the plurality of memory blocks based on whether the specific memory blocks are classified into different memory block groups or the same memory block group.

Claims (40)

1. A memory system, comprising:

a memory device including a plurality of blocks, each block having a plurality of pages to store data; and

a controller suitable for selecting specific memory blocks among the plurality memory blocks, acquiring error bit information of the plurality of pages in each of the specific memory blocks, generating a memory block group management list of each of the specific memory blocks to classify the specific memory blocks into different memory block groups or a same memory block group based on the error bit information, and performing a test read operation on the plurality of pages in each of the plurality of memory blocks based on whether the specific memory blocks are classified into different memory block groups or the same memory block group,

wherein the memory block group management list includes a group identification, a group count and an error bit information matching ratio of each of the specific memory blocks, and

wherein, when the specific memory blocks are classified in different memory block groups, the group identification is set to identify the different memory block groups, and when the specific memory block is classified into the same memory block group, the group count reflects the number of the specific blocks in the same memory block group.

2. The memory system of claim 1 , wherein the controller comprises:

a read disturbance test component suitable for selecting the specific memory blocks, and acquiring the error bit operation on the plurality of pages in each of the specific memory blocks;

a buffer memory component suitable for storing the error bit information acquired from the read disturbance test component;

a memory block group management component suitable for generating the memory block group management list of each of the specific memory blocks to classify the specific memory blocks into different memory block groups or the same memory block group based on the error bit information stored in the buffer memory component; and

a test read component suitable for performing the test read operation on the plurality of pages in each of the plurality of memory blocks based on whether the specific memory blocks are classified into different memory block groups or the same memory block group.

3. The memory system of claim 2 , wherein the memory block group management component compares the error bit information of each of the specific memory blocks to each of the other specific memory blocks, calculates an error bit information matching ratio of each of the plurality of pages in each of the specific memory blocks, compares each error bit information matching ratio with a reference error bit information matching ratio, and classifies the specific memory blocks into different memory block groups or the same different memory block group based on a comparison result.

4. The memory system of claim 3 , wherein, when the error bit information matching ratio of each of the specific memory blocks is greater than the reference error bit information matching ratio, the memory block group management component classifies the specific memory blocks into the same memory block group.

5. The memory system of claim 3 , wherein, when the error bit information matching ratio of each of the specific memory blocks is less than the reference error bit information matching ratio, the memory block group management component classifies the specific memory blocks into different memory block groups.

6. The memory system of claim 3 , wherein the memory block group management list includes a group identification, a group count and the error bit information matching ratio of each of the specific memory blocks.

7. The memory system of claim 6 , wherein, when the specific memory blocks are classified in different memory block groups, the group identification is set to reflect the different memory block groups, and when the specific memory block is classified in the same memory block group, the group count reflects the number of the specific blocks in the same memory block group.

8. The memory system of claim 2 , wherein the controller calculates an error bit information matching ratio between the plurality of pages in each of the specific memory blocks by comparing the error bit information of the plurality of pages in each of the specific memory blocks to each other, compares the error bit information matching ratio with a reference error bit information matching ratio, and classifies the specific memory blocks into different memory block groups or the same memory block group based on a comparison result.

9. The memory system according to claim 1 , wherein the controller selects a memory block group having a highest group count in the memory block management list during the test read operation, and monitors a worst page having a highest error bit information of a selected memory block group.

10. An operation method of a memory system, comprising:

acquiring error bit information of a plurality of pages in each of specific memory blocks among a plurality of memory blocks of a memory device;

generating a memory block group management list of each of the specific memory blocks to classify the specific memory blocks into different memory block groups or a same memory block group based on the error bit information; and

performing a test read operation on the plurality of pages in each of the plurality of memory blocks based on whether the specific memory blocks are classified into different memory block groups or the same memory block group,

wherein the generating of a memory block group management list includes:

comparing the error bit information of each of the specific memory blocks to each of the other specific memory blocks, and calculating an error bit information matching ratio of each of the plurality of pages in each of the specific memory blocks;

comparing each error bit information matching ratio with a reference error bit information matching ratio; and

classifying the specific memory blocks into different memory block groups or the same different memory block group based on a comparison result.

11. The operation method of the memory system of claim 10 , wherein, when the error bit information matching ratio of each of the specific memory blocks is greater than the reference error bit information matching ratio, the specific memory blocks are classified into the same memory block group.

12. The operation method of the memory system of claim 10 , wherein, when the error bit information matching ratio of each of the specific memory blocks is less than the reference error bit information matching ratio, the specific memory blocks are classified into different memory block groups.

13. The operation method of the memory system of claim 10 ,

wherein the memory block group management list includes a group identification, a group count and the error bit information matching ratio of each of the specific memory blocks,

wherein, when the specific memory blocks are classified in different memory block groups, the group identification is set to reflect the different memory block groups, and when the specific memory block is classified in the same memory block group, the group count reflects the number of the specific blocks in the same memory block group.

14. The operation method of the memory system of claim 13 , wherein during the test read operation, a memory block group having a highest group count in the memory block management list is selected, and a worst page having a highest error bit information of a selected memory block group is monitored.

15. A data processing system, comprising:

a host suitable for generating read data and a read command; and

a memory system comprising:

a memory device including a plurality of blocks, each block having a plurality of pages; and

a controller suitable for selecting specific memory blocks among the plurality memory blocks, acquiring error bit information of the plurality of pages in each of the specific memory blocks, generating a memory block group management list of each of the specific memory blocks to classify the specific memory blocks into different memory block groups or a same memory block group based on the error bit information, and performing a test read operation on the plurality of pages in each of the plurality of memory blocks based on whether the specific memory blocks are classified into different memory block groups or the same memory block,

wherein the memory block group management list includes a group identification, a group count and an error bit information matching ratio of each of the specific memory blocks,

wherein, when the specific memory blocks are classified in different memory block groups, the group identification is set to reflect the different memory block groups, and when the specific memory block is classified in the same memory block group, the group count reflects a number of the specific blocks in the same memory block group.

16. The data processing system of claim 15 , wherein the controller calculates an error bit information matching ratio between the plurality of pages in each of the specific memory blocks by comparing the error bit information of the plurality of pages in each of the specific memory blocks to each of the other specific memory blocks, compares each error bit information matching ratio with a reference error bit information matching ratio, and classifies the specific memory blocks into different memory block group or the same memory block group based on a comparison result.

17. The data processing system of claim 15 , wherein the controller selects a memory block group having a highest group count in the memory block management list during the test read operation, and monitors a worst page having a highest error bit information of a selected memory block group.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 2, 2019
From: LEE, JONG-MIN
To: SK HYNIX INC.
Reel/Frame 051153/0836 →
Priority Claims (1)
KR 10-2019-0049297 · Apr 26, 2019 · national
Continuity (1)
Related Publication 20200341890A1 · Oct 29, 2020