Masked gate logic for resistance to power analysis

1. A system comprising:

a device comprising a cryptographic circuit to perform a cryptographic operation; and

a power delivery network coupled to the device, wherein the cryptographic circuit comprises:

a mask generator circuit that determines a mask share, wherein a first portion of the mask share comprises a first number of zero-values and a second number of one-values, and a second portion of the mask share comprises the first number of one-values and the second number of zero-values; and

masked gate logic circuitry coupled to the mask generator circuit, the masked gate logic circuitry comprising a first portion and a second portion, wherein the first portion of the masked gate logic circuitry receives masked data values and the first portion of the mask share, and provides a first output, and wherein the second portion of the masked gate logic circuitry receives the masked data values and the second portion of the mask share, and provides a second output.

2. The system of claim 1 , wherein the first portion of the masked gate logic circuitry comprises a first four AND gates and a first OR gate, the first OR gate receiving outputs of the first four AND gates, and wherein the second portion of the masked gate logic circuitry comprises a second four AND gates and a second OR gate, the second OR gate receiving outputs of the second four AND gates.

3. The system of claim 1 , wherein the cryptographic circuit further comprises additional logic circuitry coupled to the masked gate logic circuitry, wherein the additional logic circuitry is to determine a final output based on the first output and the second output, wherein the final output is independent of secret data that is masked in the masked data values.

4. The system of claim 1 , wherein the cryptographic circuit further comprises additional logic circuitry coupled to the masked gate logic circuitry, wherein the additional logic circuitry is to perform an additional function on the first output and the second output before outputting a final output, wherein the final output is independent of secret data that is masked in the masked data values.

5. The system of claim 2 , wherein the output of exactly one of the first four AND gates and the second four AND gates rises, and wherein the output of the OR gate receiving the output of the AND gate that rises also rises.

6. A circuit comprising:

Boolean logic circuitry to receive cipher input values and masking values, wherein the Boolean logic circuitry outputs masked data values;

a mask generator circuit that determines a mask share, wherein a first portion of the mask share comprises a first number of zero-values and a second number of one-values, and a second portion of the mask share comprises the first number of one-values and the second number of zero-values; and

masked gate logic circuitry coupled to the mask generator circuit and the Boolean logic circuitry, the masked gate logic circuitry comprising a first portion and a second portion,

wherein the first portion of the masked gate logic circuitry:

receives the masked data values from the Boolean logic circuitry;

receives the first portion of the mask share from the mask generator circuit; and provides a first output; and

wherein the second portion of the masked gate logic circuitry:

receives the masked data values from the Boolean logic circuitry;

receives the second portion of the mask share from the mask generator circuit; and

provides a second output.

7. The circuit of claim 6 , further comprising additional Boolean logic circuitry coupled to the masked gate logic circuitry, the additional Boolean logic circuitry to:

receive the first output from the first portion of the masked gate logic circuitry;

receive the second output from the second portion of the masked gate logic circuitry; and

provide cipher output values.

8. The circuit of claim 6 , wherein the mask generator circuit comprises:

a random number generator coupled to the Boolean logic circuitry, the random number generator to generate the masking values;

a table generator coupled to the random number generator, the table generator to generate the mask share; and

a storage element coupled to the table generator and the masked gate logic circuitry, the storage element to store the mask share.

9. The circuit of claim 6 , wherein the first portion of the masked gate logic circuitry comprises a first four AND gates and a first OR gate, the first OR gate receiving outputs of the first four AND gates, and wherein the second portion of the masked gate logic circuitry comprises a second four AND gates and a second OR gate, the second OR gate receiving outputs of the second four AND gates.

10. The circuit of claim 6 , further comprising additional logic circuitry coupled to the masked gate logic circuitry, wherein the additional logic circuitry is to determine a final output based on the first output and the second output, wherein the final output is independent of the cipher input values.

11. The circuit of claim 6 , further comprising additional logic circuitry coupled to the masked gate logic circuitry, wherein the additional logic circuitry is to perform an additional function on the first output and the second output before outputting a final output, wherein the final output is independent of the cipher input values.

12. The circuit of claim 6 , further comprising a storage element coupled to the masked gate logic circuitry, the storage element to store the mask share for one or more clock cycles prior to the first portion of the masked gate logic circuitry receiving the masked data values and the first portion of the mask share.

13. The circuit of claim 6 , wherein the masked gate logic circuitry is to receive precharge signals during a first stage of a cryptographic operation, wherein the masked generator circuit is to determine the mask share during a second stage of the cryptographic operation, wherein the masked gate logic circuitry is to receive the masked data values and the mask share during a third stage of the cryptographic operation, and wherein the masked gate logic circuitry is to output the first portion and the second portion during a fourth stage of the cryptographic operation.

14. The circuit of claim 8 , wherein the storage element is a first-in-first-out (FIFO) buffer.

15. The circuit of claim 9 , wherein the output of exactly one of the first four AND gates and the second four AND gates rises, and wherein the output of the OR gate receiving the output of the AND gate that rises also rises.

16. A system comprising:

an integrated circuit comprising a set of propagation paths and a cryptographic circuit to perform a cryptographic operation; and

a power delivery network coupled to the integrated circuit, the power delivery network to delivery power to the integrated circuit, wherein the cryptographic circuit comprises:

masked gate logic circuitry that outputs output signals on each of the set of propagation paths with equal probability during the cryptographic operation to mask secret data from being detected via power analysis of the power delivery network; and

additional logic circuitry coupled to the masked gate logic circuitry, wherein the additional logic circuitry is to determine a final output based on a first output and a second output of the output signals, wherein the final output is independent of secret data that is masked in the masked data values.

17. The system of claim 16 , wherein the masked gate logic circuitry comprises:

a first portion to receive masked data values and a first portion of a mask share, the first portion to provide the first output, wherein the masked data values correspond to the secret data being masked by masking values; and

a second portion to receive the masked data values and a second portion of the mask share, the second portion to provide the second output.

18. The system of claim 17 , wherein the first portion of the masked gate logic circuitry comprises a first four AND gates and a first OR gate, the first OR gate receiving outputs of the first four AND gates, and wherein the second portion of the masked gate logic circuitry comprises a second four AND gates and a second OR gate, the second OR gate receiving outputs of the second four AND gates.

19. The system of claim 18 , wherein the output of exactly one of the first four AND gates and the second four AND gates rises, and wherein the output of the OR gate receiving the output of the AND gate that rises also rises.