Embedded very high density (VHD) layer
Embodiments may relate to an interposer that has a first layer with a plurality of first layer pads that may couple with a die. The interposer may further include a second layer with a power delivery component. The interposer may further include a very high density (VHD) layer, that has a VHD pad coupled by a first via with the power delivery component and coupled by a second via with a first layer pad. Other embodiments may be described and/or claimed.
1. An interposer comprising:
a first layer with a plurality of first layer pads, wherein a first first layer pad of the plurality of first layer pads is to couple with a first die;
a second layer with a power delivery component; and
a very high density (VHD) layer, wherein the VHD layer includes a first VHD pad and a second VHD pad of a plurality of VHD pads of the VHD layer, and wherein the first VHD pad is coupled by a first via with the power delivery component and not coupled by a via with the plurality of first layer pads, and the second VHD pad is coupled by a second via with the first first layer pad and not coupled by a via with the power delivery component.
2. The interposer of claim 1 , wherein respective pads of the plurality of VHD pads have a rectangular shape.
3. The interposer of claim 1 , wherein the first via and the second via have walls that are less than five degrees away from vertical.
4. The interposer of claim 1 , further comprising:
a third VHD pad of the plurality of VHD pads, wherein the third VHD pad is coupled with a fourth VHD pad of the plurality of VHD pads by a VHD trace;
a second first layer pad of the plurality of first layer pads, wherein the second first layer pad is coupled with the third VHD pad by a third via, and wherein the second first layer pad is to communicatively couple with the first die; and
a third first layer pad of the plurality of first layer pads, wherein the third first layer pad is coupled with the fourth VHD pad by a fourth via, and wherein the third first layer pad is to communicatively couple with a second die.
5. The interposer of claim 1 , wherein the VHD layer includes an organic dielectric material.
6. The interposer of claim 1 , wherein the VHD layer has a trace density of greater than 100 traces per millimeter.
7. The interposer of claim 1 , wherein the VHD layer is positioned between the first layer and the second layer.
8. A substrate comprising:
a first build-up (BU) layer with a plurality of first layer pads;
a second BU layer with a power delivery component; and
a very high density (VHD) layer with a plurality of VHD pads, the VHD layer positioned between the first BU layer and the second BU layer, wherein the VHD layer includes:
a first VHD pad of the plurality of VHD pads that is communicatively coupled with a first first layer pad of the plurality of first layer pads by a first via, wherein the first VHD pad is not communicatively coupled by a via to the power delivery component; and
a second VHD pad of the plurality of VHD pads that is communicatively coupled with a second first layer pad of the plurality of first layer pads by a second via and is coupled with the first VHD pad by a first VHD trace, and wherein the second VHD pad is not communicatively coupled by a via to the power delivery component.
9. The substrate of claim 8 , wherein the VHD layer includes an organic dielectric material.
10. The substrate of claim 8 , wherein the VHD layer has a trace density of greater than 100 traces per millimeter.
11. The substrate of claim 8 , wherein the first VHD pad is between 2 micrometers and 8 micrometers from the first BU layer.
12. The substrate of claim 8 , wherein the power delivery component of the second BU layer is between 10 micrometers and 40 micrometers from the VHD layer.
13. The substrate of claim 8 , wherein the power delivery component is a first power delivery component, and wherein the VHD layer includes a second power delivery component.
14. The substrate of claim 8 , wherein the VHD layer further comprises a third VHD pad of the plurality of VHD pads, and the third VHD pad is communicatively coupled with the power delivery component of the second BU layer by a third via and is not communicatively coupled by a via to the plurality of first layer pads.
15. The substrate of claim 8 , wherein respective VHD pads of the plurality of VHD pads have a rectangular shape.
16. The substrate of claim 8 , wherein the first via and the second via are lithographically defined.
17. A method of forming an interposer that includes a very high density (VHD) layer, the method comprising:
forming a second build-up (BU) layer with a power delivery component;
forming, on the second BU layer, the VHD layer, wherein the VHD layer includes a plurality of VHD pads and a first VHD pad of the plurality of VHD pads is coupled with a second VHD pad of the plurality of VHD pads by a first VHD trace, wherein the first and second VHD pads are not coupled to the power delivery component; and
forming, on the VHD layer, a first BU layer such that the VHD layer is positioned between the first BU layer and the second BU layer.
18. The method of claim 17 , further comprising lithographically forming a first via between the first BU layer and the VHD layer such that the first VHD pad is coupled with a first first layer pad of a plurality of first layer pads of the first BU layer.
19. The method of claim 17 , further comprising lithographically forming a third via between the second BU layer and the VHD layer such that when the VHD layer is formed a third VHD pad of the plurality of VHD pads is coupled with the power delivery component of the second BU layer.
20. The method of claim 19 , wherein the power delivery component is a ground or a power supply.
21. The method of claim 17 , wherein the VHD layer has a trace density of greater than 100 traces per millimeter.
22. A computing system comprising:
a substrate that includes a first build-up (BU) layer, a second BU layer with a power delivery component, and a very high density (VHD) layer positioned between the first BU layer and the second BU layer;
a first die coupled with a first first layer pad of a plurality of first layer pads of the first BU layer; and
a second die coupled with a second first layer pad of the plurality of first layer pads;
wherein the first first layer pad is coupled with a first VHD pad of a plurality of VHD pads of the VHD layer by a first via and the first VHD pad is not coupled by a via with the power delivery component;
the second first layer pad is coupled with a second VHD pad of the plurality of VHD pads by a second via and the second VHD pad is not coupled by a via to the power delivery component; and
the first VHD pad is coupled with the second VHD pad by a first VHD trace.
23. The computing system of claim 22 , wherein respective pads of the plurality of first layer pads have a rounded shape.
24. The computing system of claim 22 , wherein the VHD layer includes an organic dielectric material.
25. The computing system of claim 22 , wherein the VHD layer further includes a third VHD pad of the plurality of VHD pads coupled to the power delivery component of the second BU layer by a third via and the third VHD pad is not coupled by a via to the plurality of first layer pads of the first BU layer.