Semiconductor device
Disclosed is a semiconductor device comprising a logic cell including first and second active regions spaced apart in a first direction on a substrate, first and second active patterns on the first and second active regions and extend in a second direction, first and second source/drain patterns on the first and second active patterns, gate electrodes extending in the first direction to run across the first and second active patterns and arranged in the second direction at a first pitch, first lines in a first interlayer dielectric layer on the gate electrodes and each electrically connected to the first source/drain pattern, the second source/drain pattern, or the gate electrode, and second lines in a second interlayer dielectric layer on the first interlayer dielectric layer and extending parallel to each other in the first direction.
1. A semiconductor device, comprising:
a logic cell on a substrate, the logic cell including a first active region and a second active region spaced apart in a first direction;
a first active pattern on the first active region, and a second active pattern on the second active region, the first and second active patterns extending in a second direction that intersects the first direction;
a first source/drain pattern on an upper portion of the first active pattern and a second source/drain pattern on an upper portion of the second active pattern;
a plurality of gate electrodes that run across the first and second active patterns and extend in the first direction, the gate electrodes arranged in the second direction at a first pitch;
a plurality of first lines in a first interlayer dielectric layer on the gate electrodes, each of the first lines being electrically connected to the first source/drain pattern, the second source/drain pattern, or the gate electrode, and the first lines extending parallel to each other in the second direction; and
a plurality of second lines in a second interlayer dielectric layer on the first interlayer dielectric layer, the second lines extending parallel to each other in the first direction,
wherein
the first lines include first to third pin lines,
the second lines include first to third routing lines,
the first to third pin lines are electrically connected respectively to the first to third routing lines,
a length in the second direction of each of the first to third pin lines is less than twice the first pitch,
a first overlap region is defined where adjacent ones of the first to third pin lines overlap each other in the first direction, and
a length in the second direction of the first overlap region is less than the first pitch.
2. The semiconductor device of claim 1 , wherein
the first lines are arranged in the first direction at a second pitch,
the second lines are arranged in the second direction at a third pitch,
the third pitch is less than the first pitch, and
the third pitch is greater than the second pitch.
3. The semiconductor device of claim 2 , wherein the length in the second direction of the first overlap region is less than the third pitch.
4. The semiconductor device of claim 2 , wherein a second overlap region is defined where the first to third pin lines overlap each other in the first direction,
wherein a length in the second direction of the second overlap region is less than the third pitch.
5. The semiconductor device of claim 1 , wherein first to third lower line tracks are on a first metal layer,
wherein the first to third pin lines are respectively on the first to third lower line tracks.
6. The semiconductor device of claim 1 , wherein the logic cell has a first cell boundary and a second cell boundary opposite to the first cell boundary,
wherein the first and second cell boundaries extend in the second direction, and
wherein each of the first to third routing lines crosses the first cell boundary or the second cell boundary, the each of the first to third routing lines extending outside the logic cell.
7. The semiconductor device of claim 6 , wherein the first lines further include a first power line on the first cell boundary and a second power line on the second cell boundary.
8. The semiconductor device of claim 1 , wherein
the first lines further include a first inner line,
the second lines further include a second inner line,
one end of the second inner line is on the first active region, and other end of the second inner line is on the second active region, and
the first inner line is electrically connected to the second inner line.
9. The semiconductor device of claim 1 , further comprising a device isolation layer that covers lower sidewalls of the first and second active patterns,
wherein the upper portion of each of the first and second active patterns vertically protrudes upwards from the device isolation layer.
10. The semiconductor device of claim 1 , wherein
the first active pattern includes a plurality of first channel patterns that are vertically stacked,
the second active pattern includes a plurality of second channel patterns that are vertically stacked,
a first gate electrode of the gate electrodes is on a top surface, a bottom surface, and opposite sidewalls of each of the first channel patterns, and
a second gate electrode of the gate electrodes is on a top surface, a bottom surface, and opposite sidewalls of each of the second channel patterns.
11. A semiconductor device, comprising:
a logic cell on a substrate, the logic cell including a first active region and a second active region spaced apart in a first direction;
a first active pattern on the first active region and a second active pattern on the second active region, the first and second active patterns extending in a second direction that intersects the first direction;
a device isolation layer that covers lower sidewalls of the first and second active patterns, an upper portion of each of the first and second active patterns vertically protruding upwards from the device isolation layer;
a first source/drain pattern on the upper portion of the first active pattern and a second source/drain pattern on the upper portion of the second active pattern;
a plurality of gate electrodes that run across the first and second active patterns and extend in the first direction, the gate electrodes arranged in the second direction at a first pitch;
a plurality of first lines in a first interlayer dielectric layer on the gate electrodes, each of the first lines being electrically connected to the first source/drain pattern, the second source/drain pattern, or the gate electrode, and the first lines extending parallel to each other in the second direction; and
a plurality of second lines in a second interlayer dielectric layer on the first interlayer dielectric layer, the second lines extending parallel to each other in the first direction,
wherein
the first lines include first to third pin lines,
the second lines include first to third routing lines,
the first to third pin lines are electrically connected respectively to the first to third routing lines,
a length in the second direction of each of the first to third pin lines is less than twice the first pitch,
a first overlap region is defined where the first to third pin lines overlap each other in the first direction, and
a length in the second direction of the first overlap region is less than the first pitch.
12. The semiconductor device of claim 11 , wherein
the first lines are arranged in the first direction at a second pitch,
the second lines are arranged in the second direction at a third pitch,
the third pitch is less than the first pitch, and
the third pitch is greater than the second pitch.
13. The semiconductor device of claim 12 , wherein the length in the second direction of the first overlap region is less than the third pitch.
14. The semiconductor device of claim 11 , wherein a second overlap region is defined where adjacent ones of the first to third pin lines overlap each other in the first direction,
wherein a length in the second direction of the second overlap region is less than the first pitch.
15. The semiconductor device of claim 11 , wherein first to third lower line tracks are on a first metal layer,
wherein the first to third pin lines are respectively on the first to third lower line tracks.
16. A semiconductor device, comprising:
a logic cell on a substrate, the logic cell including a first active region and a second active region spaced apart in a first direction;
a first active pattern on the first active region and a second active pattern on the second active region, the first and second active patterns extending in a second direction that intersects the first direction, the first active pattern including a plurality of first channel patterns that are vertically stacked, and the second active pattern including a plurality of second channel patterns that are vertically stacked;
a first source/drain pattern and a second source/drain pattern, the first source/drain pattern being on one side of the first channel patterns, and the second source/drain pattern being on one side of the second channel patterns;
a plurality of gate electrodes that run across the first and second active patterns and extend in the first direction, the gate electrodes arranged in the second direction at a first pitch;
a plurality of first lines in a first interlayer dielectric layer on the gate electrodes, each of the first lines being electrically connected to the first source/drain pattern, the second source/drain pattern, or the gate electrode, and the first lines extending parallel to each other in the second direction; and
a plurality of second lines in a second interlayer dielectric layer on the first interlayer dielectric layer, the second lines extending parallel to each other in the first direction,
wherein
a first gate electrode of the gate electrodes is on a top surface, a bottom surface, and opposite sidewalls of each of the first channel patterns,
a second gate electrode of the gate electrodes is on a top surface, a bottom surface, and opposite sidewalls of each of the second channel patterns,
the first lines include first to third pin lines,
the second lines include first to third routing lines,
the first to third pin lines are electrically connected respectively to the first to third routing lines,
a length in the second direction of each of the first to third pin lines is less than twice the first pitch,
a first overlap region is defined where the first to third pin lines overlap each other in the first direction, and
a length in the second direction of the first overlap region is less than the first pitch.
17. The semiconductor device of claim 16 , wherein
the first lines are arranged in the first direction at a second pitch,
the second lines are arranged in the second direction at a third pitch,
the third pitch is less than the first pitch, and
the third pitch is greater than the second pitch.
18. The semiconductor device of claim 17 , wherein the length in the second direction of the first overlap region is less than the third pitch.
19. The semiconductor device of claim 16 , wherein a second overlap region is defined where adjacent ones of the first to third pin lines overlap each other in the first direction,
wherein a length in the second direction of the second overlap region is less than the first pitch.
20. The semiconductor device of claim 16 , wherein first to third lower line tracks are on a first metal layer,
wherein the first to third pin lines are respectively on the first to third lower line tracks.