Memory device
A memory device includes a substrate, first, second, and third conductive layers, a stack of fourth conductive layers, a memory pillar, and an insulator. The first, second, and third conductive layer are provided above the substrate. The stack of fourth conductive layers is provided above the third conductive layer. The memory pillar extends in the thickness direction through the stack and the third conductive layer and into the second conductive layer in a first region of the memory device. The insulator extends in a thickness direction through the stack, the third conductive layer, and the second conductive layer in a second region of the memory device. The insulator also extends in a second surface direction of the substrate. A thickness of the third conductive layer in a region through which the insulator extends is greater than a thickness of the third conductive layer in the first region.
1. A memory device comprising:
a substrate;
a first semiconductor layer provided above the substrate and including a first region having a first impurity concentration, a second region having a second impurity concentration above the first region, and a third region having a third impurity concentration above the second region, the second impurity concentration being higher than the first impurity concentration and the third impurity concentration;
a stacked body provided above the first semiconductor layer and including a plurality of first conductive layers stacked in a first direction;
a memory pillar extending in the first direction through the stacked body and the first semiconductor layer and having a side wall portion that is in contact with the second region of the first semiconductor layer;
a plurality of memory cells provided at intersections of the memory pillar and the plurality of first conductor layers;
an insulator extending in the first direction through the stacked body and the first semiconductor layer and in a second direction, and dividing the stacked body and the first semiconductor layer in a third direction, the second direction crossing the first direction, the third direction crossing the first direction and the second direction; and
a first insulating layer provided between a side surface of the insulator and the first, second and third regions, the first insulating layer including a portion protruding into the second region in the third direction, wherein
the third region includes a first portion that is in contact with the insulator and a second portion that is in contact with the memory pillar, and
a thickness of the first portion in the first direction is greater than a thickness of the second portion in the first direction.
2. The memory device according to claim 1 , wherein each of the first conductive layers serves as a word line of one of the plurality of memory cells.
3. The memory device according to claim 1 , wherein each of the first, second, and third regions of the first semiconductor layer is formed of poly-silicon.
4. The memory device according to claim 1 , wherein the insulator is formed of silicon oxide.
5. The memory device according to claim 1 , wherein a distance from the substrate to the memory pillar is longer than a distance from the substrate to the insulator.
6. The memory device according to claim 1 , wherein the memory pillar does not extend into the first region, and the insulator extends into the first region.
7. The memory device according to claim 1 , wherein the first insulating layer is in direct contact with the side surface of the insulator.
8. The memory device according to claim 1 , wherein the first insulating layer is also provided between a bottom surface of the insulator and the first region.
9. The memory device according to claim 8 , wherein the first insulating layer is in direct contact with the bottom surface of the insulator.
10. The memory device according to claim 1 , wherein the first insulating layer is formed of silicon oxide.
11. The memory device according to claim 1 , wherein the portion of the first insulating layer is in direct contact with the second region.
12. The memory device according to claim 1 , wherein the portion of the first insulating layer is in direct contact with the first region.
13. The memory device according to claim 1 , wherein
the second region includes a first sub-region directly provided on the first region and a second sub-region directly provided above the first sub-region, and
the second sub-region is in contact with the side surface of the first semiconductor layer.
14. The memory device according to claim 13 , wherein the first sub-region is also in contact with the side surface of the first semiconductor layer.
15. The memory device according to claim 1 , wherein the first region is in direct contact with the substrate.
16. A memory device comprising:
a substrate;
a first semiconductor layer provided above the substrate and including a first region having a first impurity concentration, a second region having a second impurity concentration above the first region, and a third region having a third impurity concentration above the second region, the second impurity concentration being higher than the first impurity concentration and the third impurity concentration;
a stacked body provided above the first semiconductor layer and including a plurality of first conductive layers stacked in a first direction;
a memory pillar extending in the first direction through the stacked body and the first semiconductor layer and having a side wall portion that is in contact with the second region of the first semiconductor layer;
a plurality of memory cells provided at intersections of the memory pillar and the plurality of first conductor layers; and
an insulator extending in the first direction through the stacked body and the first semiconductor layer and in a second direction, and dividing the stacked body and the first semiconductor layer in a third direction, the second direction crossing the first direction, the third direction crossing the first direction and the second direction, wherein
the third region includes a first portion that is in contact with the insulator and a second portion that is in contact with the memory pillar,
a thickness of the first portion in the first direction is greater than a thickness of the second portion in the first direction,
the second region includes a first sub-region directly provided on the first region and a second sub-region directly provided above the first sub-region, and
the second sub-region is in contact with the side surface of the first semiconductor layer.
17. The memory device according to claim 16 , wherein the first sub-region is also in contact with the side surface of the first semiconductor layer.