Multi threshold voltage for nanosheet
A semiconductor structure including nanosheet stacks on a substrate, each nanosheet stack including alternating layers of sacrificial semiconductor material and semiconductor channel material and a crystallized gate dielectric layer surrounding the semiconductor channel layers of a first subset of the nanosheet stacks, a dipole layer on top of the crystallized gate dielectric and surrounding the layers of semiconductor channel material of the first subset of the nanosheet stacks and a gate dielectric modified by a diffused dipole material surrounding the semiconductor channel layers of a second subset of the nanosheet stacks. A method including forming nanosheet stacks on a substrate, each nanosheet stack including alternating layers of sacrificial semiconductor material and semiconductor channel material, removing sacrificial semiconductor material layers of the set of nanosheet stacks, forming a gate dielectric surrounding the semiconductor channel layers of the nanosheet stacks, and crystalizing the gate dielectric of a subset of the nanosheet stacks.
1. A semiconductor structure comprising:
nanosheet stacks on a substrate, each nanosheet stack comprising alternating layers of a sacrificial semiconductor material and a semiconductor channel material vertically aligned and stacked one on top of another; and
a crystallized gate dielectric layer surrounding the layers of semiconductor channel material of a first subset of the nanosheet stacks, wherein the crystallized gate dielectric layer directly contacts and covers shallow trench isolation regions between adjacent nanosheet stacks;
a dipole layer on top of the crystallized gate dielectric layer and surrounding the layers of semiconductor channel material of the first subset of the nanosheet stacks; and
a gate dielectric modified by a diffused dipole material surrounding the layers of semiconductor channel material of a second subset of the nanosheet stacks.
2. The semiconductor structure according to claim 1 , further comprising:
a first gate conductor layer orthogonal to the nanosheet stacks, the first gate conductor layer wraps around the layers of semiconductor channel material of the nanosheet stacks.
3. The semiconductor structure according to claim 1 , wherein crystallizing the gate dielectric comprises annealing the gate dielectric to form the crystallized gate dielectric layer.
4. The semiconductor structure according to claim 1 , wherein the layers of sacrificial semiconductor material comprise silicon germanium.
5. The semiconductor structure according to claim 1 , further comprising:
source drain regions extending laterally from either end of the layers of semiconductor channel material of the nanosheet stacks.
6. A semiconductor structure comprising:
nanosheet stacks on a substrate, each nanosheet stack comprising alternating layers of a sacrificial semiconductor material and a semiconductor channel material vertically aligned and stacked one on top of another; and
a crystallized gate dielectric layer surrounding the layers of semiconductor channel material of the nanosheet stacks, wherein the crystallized gate dielectric layer directly contacts and covers shallow trench isolation regions between adjacent nanosheet stacks.
7. The semiconductor structure according to claim 6 , further comprising:
a dipole layer on top of the crystallized gate dielectric layer and surrounding the layers of semiconductor channel material of a subset of the nanosheet stacks.
8. The semiconductor structure according to claim 6 , further comprising:
a first gate conductor layer orthogonal to the nanosheet stacks, the first gate conductor layer wraps around the layers of semiconductor channel material of the nanosheet stacks.
9. The semiconductor structure according to claim 6 , wherein
crystallizing the gate dielectric comprises annealing the gate dielectric to form the crystallized gate dielectric layer.
10. The semiconductor structure according to claim 6 , wherein the layers of sacrificial semiconductor material comprise silicon germanium.
11. The semiconductor structure according to claim 6 , further comprising:
source drain regions extending laterally from either end of the layers of semiconductor channel material of the nanosheet stacks.
12. A method comprising:
forming nanosheet stacks on a substrate, each nanosheet stack comprising alternating layers of a sacrificial semiconductor material and a semiconductor channel material vertically aligned and stacked one on top of another;
removing the layers of sacrificial semiconductor material of the set of nanosheet stacks;
forming a gate dielectric surrounding the layers of semiconductor channel material of the nanosheet stacks; and
crystalizing the gate dielectric of a first subset of the nanosheet stacks, wherein the crystallized gate dielectric layer directly contacts and covers shallow trench isolation regions between adjacent nanosheet stacks.
13. The method according to claim 12 , further comprising:
forming a dipole layer surrounding the gate dielectric which surrounds the layers of semiconductor channel material of a second subset of the nanosheet stacks.
14. The method according to claim 13 , further comprising:
diffusing the dipole layer into the gate dielectric surrounding the layers of semiconductor channel material of the second subset of the nanosheet stacks.
15. The method according to claim 12 , further comprising:
forming a first gate conductor layer orthogonal to the nanosheet stacks, the first gate conductor wraps around the layers of semiconductor channel material of the nanosheet stacks.
16. The method according to claim 12 , wherein crystallizing the gate dielectric comprises annealing the gate dielectric to form the crystallized gate dielectric layer.
17. The method according to claim 12 , wherein the layer of sacrificial semiconductor material comprise silicon germanium.
18. The method according to claim 12 , further comprising:
forming source drain regions extending laterally from either end of the semiconductor channel material layers of the nanosheet stacks.