IP Library Granted Patent US 12,733,229
Granted Patent B2
US 12,733,229 · App. 18/065,660 · Granted Sep 8, 2026

Nanoribbon stacks without dielectric protection caps for top nanoribbons

Inventors: Rohit Galatage (Hillsboro, OR); Cheng-Ying Huang (Portland, OR); Jack T. Kavalieros (Portland, OR); Marko Radosavljevic (Portland, OR); Mauro J. Kobrinsky (Portland, OR); Jami Wiedemer (Scappoose, OR); Munzarin Qayyum (Hillsboro, OR); Evan Clinton (Carrollton, GA)
Assignee: Intel Corporation
H10D64/01H10D30/014H10D30/031H10D30/43H10D30/6735H10D64/015H10D30/6736
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 12,733,229
App. No.
18/065,660
Granted
Sep 8, 2026
Kind
B2
Abstract

IC structures with nanoribbon stacks without dielectric protection caps for top nanoribbons, and associated methods and devices, are disclosed. An example IC structure includes a stack of nanoribbons, an opening over the top nanoribbon of the stack of nanoribbons, and a gate electrode material in the opening, where the opening has a first portion, a second portion, and a third portion, the second portion is between the first portion and the third portion, and where a width of a portion of the gate electrode material in the second portion is smaller than a width of a portion of the gate electrode material in the first portion. In such an IC structure, a gate insulator on the sidewalls of the first portion of the opening is materially discontinuous from a gate insulator on the sidewalls of the third portion of the opening.

Claims (52)

1 . An integrated circuit (IC) structure, comprising:

a base;

a stack of nanoribbons over the base; and

an opening over a top nanoribbon of the stack, the opening comprising a first portion, a second portion, and a third portion, wherein:

the first portion is closer to the base than the second portion,

the second portion is closer to the base than the third portion, and

a gate insulator is on sidewalls of the first portion and the third portion and is absent from sidewalls of the second portion.

2 . The IC structure according to claim 1 , wherein a width of the second portion is smaller than a width of at least a part of the first portion.

3 . The IC structure according to claim 1 , wherein a width of the second portion is smaller than a width of at least a part of the third portion.

4 . The IC structure according to claim 1 , further comprising a work function material over the sidewalls of the opening, wherein:

the gate insulator on the sidewalls of the first portion is between the sidewalls of the first portion and a portion of the work function material over the sidewalls of the first portion, and

the gate insulator on the sidewalls of the third portion is between the sidewalls of the third portion and a portion of the work function material over the sidewalls of the third portion.

5 . The IC structure according to claim 4 , further comprising a gate electrode material in the opening, wherein:

a portion of the work function material over the sidewalls of the second portion is between the sidewalls of the second portion and a portion of the gate electrode material in the second portion.

6 . The IC structure according to claim 5 , wherein the portion of the work function material over the sidewalls of the first portion, the portion of the work function material over the sidewalls of the second portion, and the portion of the work function material over the sidewalls of the third portion are portions of a materially continuous work function material.

7 . The IC structure according to claim 6 , wherein the materially continuous work function material has a U-shaped cross-section in the first portion.

8 . The IC structure according to claim 5 , wherein:

the portion of the work function material over the sidewalls of the first portion is between the sidewalls of the first portion and a portion of the gate electrode material in the first portion, and

the portion of the work function material over the sidewalls of the third portion is between the sidewalls of the third portion and a portion of the gate electrode material in the third portion.

9 . The IC structure according to claim 5 , wherein a width of the portion of the gate electrode material in the second portion is smaller than a width of a portion of the gate electrode material in the first portion and a width of a portion of the gate electrode material in the third portion.

10 . The IC structure according to claim 9 , wherein the portion of the gate electrode material in the first portion, the portion of the gate electrode material in the second portion, and the portion of the gate electrode material in the third portion are portions of a materially continuous gate electrode material.

11 . An integrated circuit (IC) structure, comprising:

a support;

a stack of nanoribbons over the support;

an opening over a top nanoribbon of the stack; and

a gate electrode material in the opening,

wherein:

the opening has a first portion, a second portion, and a third portion,

the second portion is between the first portion and the third portion, and

a width of a portion of the gate electrode material in the second portion is smaller than a width of a portion of the gate electrode material in the first portion.

12 . The IC structure according to claim 11 , wherein the width of the portion of the gate electrode material in the second portion is smaller than a width of a portion of the gate electrode material in the third portion.

13 . The IC structure according to claim 12 , wherein the portion of the gate electrode material in the first portion, the portion of the gate electrode material in the second portion, and the portion of the gate electrode material in the third portion are portions of a materially continuous gate electrode material.

14 . The IC structure according to claim 11 , further comprising:

a first gate insulator on a bottom and sidewalls of the first portion, and

a second gate insulator on sidewalls of the third portion,

wherein the first gate insulator is materially discontinuous from the second gate insulator.

15 . The IC structure according to claim 14 , further comprising a work function material, wherein:

a first portion of the work function material is a liner of the work function material between the first gate insulator on the bottom and the sidewalls of the first portion and the portion of the gate electrode material in the first portion,

a second portion of the work function material is a liner of the work function material between sidewalls of the second portion and the portion of the gate electrode material in the second portion, and

a third portion of the work function material is a liner of the work function material between the second gate insulator on the sidewalls of the third portion and the portion of the gate electrode material in the third portion.

16 . The IC structure according to claim 15 , wherein a thickness of the liner of the first portion of the work function material and a thickness of the liner of the second portion of the work function material are substantially equal.

17 . The IC structure according to claim 15 , wherein the first, second, and third portions of the work function material are portions of a materially continuous work function material.

18 . A process of making an integrated circuit (IC) structure, the process comprising:

providing a stack of nanoribbons over a base; and

providing an opening over a top nanoribbon of the stack, the opening comprising a first portion, a second portion, and a third portion, wherein:

the first portion is closer to the base than the second portion,

the second portion is closer to the base than the third portion, and

a gate insulator is on sidewalls of the first portion and the third portion and is absent from sidewalls of the second portion.

19 . The process according to claim 18 , wherein:

a width of the second portion is smaller than a width of at least a part of the first portion.

20 . The process according to claim 18 , wherein:

a width of the second portion is smaller than a width of at least a part of the third portion.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 14, 2026
From: INTEL CORPORATION
To: INTEL FOUNDRY IP LLC
Reel/Frame 076007/0292 →
CORRECTIVE ASSIGNMENT TO CORRECT THE ERRONEOUS APPLICATION NUMBER 08065660 WHICH SHOULD BE APPLICATION NUMBER 18065660 PREVIOUSLY RECORDED AT REEL: 064014 FRAME: 0150. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Nov 1, 2023
From: GALATAGE, ROHIT; HUANG, CHENG-YING; KAVALIEROS, JACK T.; RADOSAVLJEVIC, MARKO; KOBRINSKY, MAURO J.; WIEDEMER, JAMI; QAYYUM, MUNZARIN; CLINTON, EVAN
To: INTEL CORPORATION
Reel/Frame 065425/0388 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 14, 2022
From: GALATAGE, ROHIT; HUANG, CHENG-YING; KAVALIEROS, JACK T.; RADOSAVLJEVIC, MARKO; KOBRINSKY, MAURO J.; WIEDEMER, JAMI; QAYYUM, MUNZARIN; CLINTON, EVAN
To: INTEL CORPORATION
Reel/Frame 064014/0150 →
Continuity (1)
Related Publication 20240204060A1 · Jun 20, 2024
References Cited (6)
US 11387342B1 · Zhang et al. · 2022 [cited by applicant]
US 20210408246A1 · Ganguly · 2021 [cited by examiner]
US 20220093474A1 · Mishra et al. · 2022 [cited by applicant]
US 20220093747A1 · Ohno · 2022 [cited by examiner]
US 20220399445A1 · Guler · 2022 [cited by examiner]
Weckx, P., et al., “Novel Forksheet Device Architecture As Ultimate Logic Scaling Device Towards 2nm,” IEEE; 4 pages (2019). [cited by applicant]