Secure boot hardware including hardware serial presence detection
Techniques in electronic systems, such as in systems including a processing chip and one or more external memory chips, provide improvements in one or more of system security, performance, cost, and efficiency. For example, the processing chip includes one or more CPUs and circuitry enabling the CPUs to securely boot from an external, non-volatile memory chip containing encrypted, executable code. The circuitry comprises immutable hardware to hold the CPUs in a reset state while performing a serial presence detect on external interfaces of the processing chip and generating an address map according to results of the serial presence detect. In response to an initial instruction fetch of an initial one of the CPUs, the circuitry is able to return one or more instructions via the address map associating an address of the initial instruction fetch with one of the external memory chips.
1. A system, comprising: an integrated circuit comprising one or more central processing units (CPUs) and hardware, wherein the hardware comprises immutable hardware that does not contain any run-time programmable CPUs; and memory chips, wherein the hardware comprises one or more external memory interfaces that are coupled to a respective one or more of the memory chips; wherein the immutable hardware is configured to perform, based at least in part on a reset signal, a hardware portion of a boot sequence; and wherein the hardware portion of the boot sequence comprises: holding the one or more CPUs in a reset state in which the one or more CPUs are not able to commence or complete a respective initial instruction fetch; performing a Serial Presence Detect (SPD) operation on the one or more external memory interfaces to determine or confirm respective configuration information of the respective one or more of the memory chips; generating at least a portion of an address map based at least in part on at least some of the respective configuration information; and subsequent to the generating the at least the portion of the address map, releasing the reset state on an initial one of the one or more CPUs, wherein the immutable hardware is configured to return one or more instructions in response to the respective initial instruction fetch of the initial one of the one or more CPUs via the address map by associating an address of the respective initial instruction fetch of the initial one of the one or more CPUs with a particular one or more of the memory chips; and wherein the immutable hardware further comprises one or more keys; wherein the immutable hardware is configured to return the one or more instructions by performing operations comprising reading initial data from a non-volatile one or more of the memory chips; wherein the one or more instructions are obtainable by decrypting the initial data using a specific one of the one or more keys; and wherein the immutable hardware, without involvement of the one or more CPUs, is configured to perform the hardware portion of the boot sequence and the return of the one or more instructions.
2. The system of claim 1 , wherein the hardware portion of the boot sequence is not alterable by the one or more CPUs.
3. The system of claim 1 , wherein the performing the hardware portion of the boot sequence further comprises:
copying, without decrypting, encrypted executable code comprising the initial data from the non-volatile one or more of the memory chips to the particular one or more of the memory chips.
4. The system of claim 1 , wherein the performing the hardware portion of the boot sequence further comprises:
reading encrypted executable code comprising the initial data from the non-volatile one or more of the memory chips;
decrypting the encrypted executable code using the specific one of the one or more keys;
re-encrypting the decrypted executable code using a particular one of the one or more keys that is different from the specific one of the one or more keys or a key-less scrambling technique; and
writing the re-encrypted executable code to the particular one or more of the memory chips.
5. The system of claim 1 , wherein the non-volatile one or more of the memory chips are inaccessible by software executing on the one or more CPUs.
6. The system of claim 1 , wherein the performing the hardware portion of the boot sequence further comprises:
performing an integrity check on contents of the non-volatile one or more of the memory chips; and
in response to a failure of the integrity check, aborting the hardware portion of the boot sequence.
7. The system of claim 1 , wherein the immutable hardware comprises expected configuration information; and
wherein the performing the hardware portion of the boot sequence further comprises:
confirming at least some of the respective configuration information by comparing at least some results of the SPD operation with the expected configuration information.
8. The system of claim 1 , wherein the integrated circuit comprises a securely-bootable subsystem, and the securely-bootable subsystem comprises the one or more CPUs and the hardware comprising the immutable hardware configured to perform the hardware portion of the boot sequence and to return the one or more instructions.
9. The system of claim 8 , wherein the one or more CPUs comprise all of the run-time programmable CPUs in the securely-bootable subsystem.
10. A method for performing a hardware portion of boot sequence, comprising: by a system that comprises an integrated circuit and memory chips, wherein the integrated circuit comprises one or more central processing units (CPUs) and hardware, wherein the hardware comprises immutable hardware that does not contain any run-time programmable CPUs, and wherein the hardware comprises one or more external memory interfaces that are coupled to a respective one or more of the memory chips: receiving a reset signal; and performing, using the immutable hardware and based at least in part on a reset signal, the hardware portion of a boot sequence, wherein the hardware portion of the boot sequence comprises: holding the one or more CPUs in a reset state in which the one or more CPUs are not able to commence or complete a respective initial instruction fetch; performing a Serial Presence Detect (SPD) operation on the one or more external memory interfaces to determine or confirm respective configuration information of the respective one or more of the memory chips; generating at least a portion of an address map based at least in part on at least some of the respective configuration information; and subsequent to the generating the at least the portion of the address map, releasing the reset state on an initial one of the one or more CPUs, wherein the immutable hardware returns one or more instructions in response to the respective initial instruction fetch of the initial one of the one or more CPUs via the address map by associating an address of the respective initial instruction fetch of the initial one of the one or more CPUs with a particular one or more of the memory chips; and
wherein the immutable hardware further comprises one or more keys; wherein the immutable hardware returns the one or more instructions based at least in part on the respective initial instruction fetch of the initial one of the one or more CPUs by performing operations comprising reading initial data from a non-volatile one or more of the memory chips; wherein the one or more instructions are obtainable by decrypting the initial data using a specific one of the one or more keys; and wherein the immutable hardware, without involvement of the one or more CPUs, performs the hardware portion of the boot sequence and the return of the one or more instructions.
11. The method of claim 10 , wherein the hardware portion of the boot sequence is not alterable by the one or more CPUs.
12. The method of claim 10 , wherein the performing the hardware portion of the boot sequence further comprises:
copying, without decrypting, encrypted executable code comprising the initial data from the non-volatile one or more of the memory chips to the particular one or more of the memory chips.
13. The method of claim 10 , wherein the performing the hardware portion of the boot sequence further comprises:
reading encrypted executable code comprising the initial data from the non-volatile one or more of the memory chips;
decrypting the encrypted executable code using the specific one of the one or more keys;
re-encrypting the decrypted executable code using a particular one of the one or more keys that is different from the specific one of the one or more keys or a key-less scrambling technique; and
writing the re-encrypted executable code to the particular one or more of the memory chips.
14. The method of claim 10 , wherein the non-volatile one or more of the memory chips are inaccessible by software executing on the one or more CPUs.
15. The method of claim 10 , wherein the performing the hardware portion of the boot sequence further comprises:
performing an integrity check on contents of the non-volatile one or more of the memory chips; and
in response to a failure of the integrity check, aborting the hardware portion of the boot sequence.
16. The method of claim 10 , wherein the immutable hardware comprises expected configuration information; and
wherein the performing the hardware portion of the boot sequence further comprises:
confirming at least some of the respective configuration information by comparing at least some results of the SPD operation with the expected configuration information.
17. The method of claim 10 , wherein the integrated circuit comprises a securely-bootable subsystem, and the securely-bootable subsystem comprises the one or more CPUs and the hardware comprising the immutable hardware that performs the hardware portion of the boot sequence and returns the one or more instructions.
18. An integrated circuit, comprising: one or more central processing units (CPUs); immutable hardware that does not contain any run-time programmable CPUs; and one or more external memory interfaces that are configured to couple to a respective one or more of memory chips; wherein the immutable hardware is configured to perform, based at least in part on a reset signal, a hardware portion of a boot sequence; and wherein the hardware portion of the boot sequence comprises: holding the one or more CPUs in a reset state in which the one or more CPUs are not able to commence or complete a respective initial instruction fetch; performing a Serial Presence Detect (SPD) operation on the one or more external memory interfaces to determine or confirm respective configuration information of the respective one or more of the memory chips; generating at least a portion of an address map based at least in part on at least some of the respective configuration information; and subsequent to the generating the at least the portion of the address map, releasing the reset state on an initial one of the one or more CPUs, wherein the immutable hardware is configured to return one or more instructions in response to the respective initial instruction fetch of the initial one of the one or more CPUs via the address map by associating an address of the respective initial instruction fetch of the initial one of the one or more CPUs with a particular one or more of the memory chips; and wherein the immutable hardware further comprises one or more keys; wherein the immutable hardware returns the one or more instructions based at least in part on the respective initial instruction fetch of the initial one of the one or more CPUs by performing operations comprising reading initial data from a non-volatile one or more of the memory chips; wherein the one or more instructions are obtainable by decrypting the initial data using a specific one of the one or more keys; and wherein the immutable hardware, without involvement of the one or more CPUs, performs the hardware portion of the boot sequence and the return of the one or more instructions.