Apparatuses, methods, and systems to precisely monitor memory store accesses
Systems, methods, and apparatuses relating to circuitry to precisely monitor memory store accesses are described. In one embodiment, a system includes a memory, a hardware processor core comprising a decoder to decode an instruction into a decoded instruction, an execution circuit to execute the decoded instruction to produce a resultant, a store buffer, and a retirement circuit to retire the instruction when a store request for the resultant from the execution circuit is queued into the store buffer for storage into the memory, and a performance monitoring circuit to mark the retired instruction for monitoring of post-retirement performance information between being queued in the store buffer and being stored in the memory, enable a store fence after the retired instruction to be inserted that causes previous store requests to complete within the memory, and on detection of completion of the store request for the instruction in the memory, store the post-retirement performance information in storage of the performance monitoring circuit.
1. An apparatus comprising:
a memory;
a hardware processor core comprising:
a decoder to decode an instruction into a decoded instruction,
an execution circuit to execute the decoded instruction to produce a resultant,
a store buffer, and
a retirement circuit to retire the instruction when a store request for the resultant from the execution circuit is queued into the store buffer for storage into the memory but is not yet completed within the memory; and
a performance monitoring circuit to:
mark the retired instruction for monitoring of post-retirement performance information between being queued in the store buffer and being stored in the memory,
enable, when the instruction to which the store request belongs completes execution, a store fence after the retired instruction to be inserted that causes previous store requests to complete within the memory, and
on detection of completion of the store request for the instruction in the memory, store the post-retirement performance information in storage of the performance monitoring circuit.
2. The apparatus of claim 1 , wherein the instruction comprises a plurality of store requests, and the performance monitoring circuit is to enable the store fence for the retired instruction to be inserted after a last store request of the plurality of store requests is queued into the store buffer.
3. The apparatus of claim 1 , wherein the memory is a cache of the hardware processor core, and when the store request leaves the store buffer for completion in the cache, the performance monitoring circuit is to enable a counter to measure a latency between the store request leaving the store buffer and completion in the cache.
4. The apparatus of claim 3 , wherein the cache is a next level cache, and the post-retirement performance information indicates a miss for the store request in a previous level cache.
5. The apparatus of claim 1 , wherein the memory is separate from a cache of the hardware processor core, a fill buffer is to queue the store request when the store request misses in the cache for servicing by the memory, and when the store request leaves the store buffer for completion in the memory, the performance monitoring circuit is to enable a counter to measure a latency between the store request leaving the store buffer and completion in the memory.
6. The apparatus of claim 5 , wherein the cache is a last level cache of a processor comprising the hardware processor core.
7. The apparatus of claim 1 , wherein the performance monitoring circuit comprises a sampling counter to cause marking of the retired instruction for monitoring after a threshold number of instructions are retired.
8. The apparatus of claim 1 , wherein the storage of the performance monitoring circuit is a software visible register.
9. A method comprising:
decoding an instruction into a decoded instruction with a decoder of a hardware processor core;
executing the decoded instruction with an execution circuit of the hardware processor core to produce a resultant;
retiring the instruction with a retirement circuit of the hardware processor core when a store request for the resultant from the execution circuit is queued into a store buffer for storage into memory but is not yet completed within the memory;
marking the retired instruction, by a performance monitoring circuit, for monitoring of post-retirement performance information between being queued in the store buffer and being stored in the memory;
inserting a store fence after the retired instruction, by the performance monitoring circuit when the instruction to which the store request belongs completes execution, that causes previous store requests to complete within the memory; and
storing the post-retirement performance information in storage of the performance monitoring circuit on detection of completion of the store request in the memory for the instruction.
10. The method of claim 9 , wherein the instruction comprises a plurality of store requests, and inserting comprises the performance monitoring circuit inserting the store fence for the retired instruction after a last store request of the plurality of store requests is queued into the store buffer.
11. The method of claim 9 , wherein the memory is a cache of the hardware processor core, and further comprising enabling a counter of the performance monitoring circuit, when the store request leaves the store buffer for completion in the cache, to measure a latency between the store request leaving the store buffer and completion in the cache.
12. The method of claim 11 , wherein the cache is a next level cache, and the post-retirement performance information indicates a miss for the store request in a previous level cache.
13. The method of claim 9 , wherein the memory is separate from a cache of the hardware processor core, and further comprising:
queuing the store request in a fill buffer of the hardware processor core, when the store request misses in the cache, for servicing by the memory; and
enabling a counter of the performance monitoring circuit, when the store request leaves the store buffer for completion in the memory, to measure a latency between the store request leaving the store buffer and completion in the memory.
14. The method of claim 13 , wherein the cache is a last level cache of a processor comprising the hardware processor core.
15. The method of claim 9 , further comprising:
enabling a counter of the performance monitoring circuit to count a number of instructions that are retired; and
marking the retired instruction for monitoring after the counter exceeds a threshold number of instructions that have been retired.
16. The method of claim 9 , wherein the storage of the performance monitoring circuit is a software visible register.
17. A non-transitory machine readable medium that stores code that when executed by a machine causes the machine to perform a method comprising:
decoding an instruction into a decoded instruction with a decoder of a hardware processor core;
executing the decoded instruction with an execution circuit of the hardware processor core to produce a resultant;
retiring the instruction with a retirement circuit of the hardware processor core when a store request for the resultant from the execution circuit is queued into a store buffer for storage into memory but is not yet completed within the memory;
marking the retired instruction, by a performance monitoring circuit, for monitoring of post-retirement performance information between being queued in the store buffer and being stored in the memory;
inserting a store fence after the retired instruction, by the performance monitoring circuit when the instruction to which the store request belongs completes execution, that causes previous store requests to complete within the memory; and
storing the post-retirement performance information in storage of the performance monitoring circuit on detection of completion of the store request in the memory for the instruction.
18. The non-transitory machine readable medium of claim 17 , wherein the instruction comprises a plurality of store requests, and inserting comprises the performance monitoring circuit inserting the store fence for the retired instruction after a last store request of the plurality of store requests is queued into the store buffer.
19. The non-transitory machine readable medium of claim 17 , wherein the memory is a cache of the hardware processor core, and further comprising enabling a counter of the performance monitoring circuit, when the store request leaves the store buffer for completion in the cache, to measure a latency between the store request leaving the store buffer and completion in the cache.
20. The non-transitory machine readable medium of claim 19 , wherein the cache is a next level cache, and the post-retirement performance information indicates a miss for the store request in a previous level cache.
21. The non-transitory machine readable medium of claim 17 , wherein the memory is separate from a cache of the hardware processor core, and further comprising:
queuing the store request in a fill buffer of the hardware processor core, when the store request misses in the cache, for servicing by the memory; and
enabling a counter of the performance monitoring circuit, when the store request leaves the store buffer for completion in the memory, to measure a latency between the store request leaving the store buffer and completion in the memory.
22. The non-transitory machine readable medium of claim 21 , wherein the cache is a last level cache of a processor comprising the hardware processor core.
23. The non-transitory machine readable medium of claim 17 , further comprising:
enabling a counter of the performance monitoring circuit to count a number of instructions that are retired; and
marking the retired instruction for monitoring after the counter exceeds a threshold number of instructions that have been retired.
24. The non-transitory machine readable medium of claim 17 , wherein the storage of the performance monitoring circuit is a software visible register.