IP Library › Granted Patent US 11,393,156
Granted Patent B2
US 11,393,156 · App. 16/819,014 · Granted Jul 19, 2022

Partially resident bounding volume hierarchy

Inventors: Skyler Jonathon Saleh (San Diego, CA); Fataneh Ghodrat (Boxborough, MA)
Assignee: Advanced Micro Devices, Inc.
G06T15/06G06K9/6279G06T1/60G06T15/005G06T17/10
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Quick Facts
Patent No.
US 11,393,156
App. No.
16/819,014
Granted
Jul 19, 2022
Kind
B2
Abstract

Techniques for performing ray tracing for a ray are provided. The techniques include, based on first traversal of a bounding volume hierarchy, identifying a first memory page that is classified as resident, obtaining a first portion of the bounding volume hierarchy associated with the first memory page, traversing the first portion of the bounding volume hierarchy according to a ray intersection test, based on second traversal of the bounding volume hierarchy, identifying a second memory page that is classified as valid and non-resident, and in response to the second memory page being classified as valid and non-resident, determining that a miss occurs for each node of the bounding volume hierarchy within the second memory page.

Claims (60)

1. A method for performing ray tracing for a ray, the method comprising:

based on first traversal of a bounding volume hierarchy, identifying a first memory page that is classified as resident according to a page table;

obtaining a first portion of the bounding volume hierarchy associated with the first memory page;

traversing the first portion of the bounding volume hierarchy according to a ray intersection test;

based on second traversal of the bounding volume hierarchy, identifying a second memory page that is classified as valid and non-resident according to the page table;

in response to the second memory page being classified as valid and nonresident, processing as if a miss occurs for each node of the bounding volume hierarchy within the second memory page.

2. The method of claim 1 , wherein the first traversal of the bounding volume hierarchy comprises:

determining that the ray intersects with a first parent node that is a parent of one or more nodes of the first memory page; and

obtaining a page address for the one or more nodes from within data of the first parent node.

3. The method of claim 2 , wherein identifying the first memory page that is classified as resident comprises:

determining that the page address is indicated as being resident according to the page table.

4. The method of claim 1 , wherein the second traversal of the bounding volume hierarchy comprises:

determining that the ray intersects with a second parent node that is a parent of one or more nodes of the second memory page; and

obtaining a page address for the one or more nodes from within data of the second parent node.

5. The method of claim 4 , wherein identifying the second memory page that is classified as valid and non-resident comprises:

determining that the page address is indicated as being valid and non-resident according to the page table.

6. The method of claim 1 , further comprising:

based on third traversal of the bounding volume hierarchy, identifying a third memory page that is classified as invalid; and

generating a fault for the third memory page.

7. The method of claim 1 , further comprising:

in response to determining that the miss occurs for each node of the bounding volume hierarchy within the second memory page, executing no hit shader for any triangle node that is a descendant of any node within the second memory page.

8. The method of claim 1 , further comprising:

in response to determining that processing is to occur as if a miss occurs for each node of the bounding volume hierarchy within the second memory page, executing a miss shader for the ray.

9. The method of claim 1 , further comprising:

updating the status of memory pages of the bounding volume hierarchy based on migration of the memory pages.

10. A system for performing ray tracing for a ray, the system comprising:

a memory storing memory pages of a bounding volume hierarchy; and a processor configured to:

based on first traversal of a bounding volume hierarchy, identify a first memory page that is classified as resident according to a page table;

obtain a first portion of the bounding volume hierarchy associated with the first memory page;

traverse the first portion of the bounding volume hierarchy according to a ray intersection test;

based on second traversal of the bounding volume hierarchy, identify a second memory page that is classified as valid and non-resident according to the page table;

in response to the second memory page being classified as valid and nonresident, processing as if a miss occurs for each node of the bounding volume hierarchy within the second memory page.

11. The system of claim 10 , wherein the first traversal of the bounding volume hierarchy comprises:

determining that the ray intersects with a first parent node that is a parent of one or more nodes of the first memory page; and

obtaining a page address for the one or more nodes from within data of the first parent node.

12. The system of claim 11 , wherein identifying the first memory page that is classified as resident comprises:

determining that the page address is indicated as being resident according to the page table.

13. The system of claim 10 , wherein the second traversal of the bounding volume hierarchy comprises:

determining that the ray intersects with a second parent node that is a parent of one or more nodes of the second memory page; and

obtaining a page address for the one or more nodes from within data of the second parent node.

14. The system of claim 13 , wherein identifying the second memory page that is classified as valid and non-resident comprises:

determining that the page address is indicated as being valid and non-resident according to the page table.

15. The system of claim 10 , wherein the processor is further configured to:

based on third traversal of the bounding volume hierarchy, identify a third memory page that is classified as invalid; and

generate a fault for the third memory page.

16. The system of claim 10 , wherein the processor is further configured to:

in response to determining that the miss occurs for each node of the bounding volume hierarchy within the second memory page, execute no hit shader for any triangle node that is a descendant of any node within the second memory page.

17. The system of claim 10 , wherein the processor is further configured to:

in response to determining that processing is to occur as if a miss occurs for each node of the bounding volume hierarchy within the second memory page, execute a miss shader for the ray.

18. The system of claim 10 , wherein the processor is further configured to:

update the status of memory pages of the bounding volume hierarchy based on migration of the memory pages.

19. A non-transitory computer-readable medium storing instructions that, when executed by a processor, cause the processor to perform ray tracing for a ray, by:

based on first traversal of a bounding volume hierarchy, identifying a first memory page that is classified as resident according to a page table;

obtaining a first portion of the bounding volume hierarchy associated with the first memory page;

traversing the first portion of the bounding volume hierarchy according to a ray intersection test;

based on second traversal of the bounding volume hierarchy, identifying a second memory page that is classified as valid and non-resident according to the page table;

in response to the second memory page being classified as valid and nonresident, processing as if a miss occurs for each node of the bounding volume hierarchy within the second memory page.

20. The non-transitory computer-readable medium of claim 19 , wherein the first traversal of the bounding volume hierarchy comprises:

determining that the ray intersects with a first parent node that is a parent of one or more nodes of the first memory page; and

obtaining a page address for the one or more nodes from within data of the first parent node.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 9, 2020
From: SALEH, SKYLER JONATHON; GHODRAT, FATANEH
To: ADVANCED MICRO DEVICES, INC.
Reel/Frame 052886/0679 →
Continuity (1)
Related Publication 20210287422A1 · Sep 16, 2021