Semiconductor memory device
A semiconductor memory device includes a plurality of memory cells, a word line connected to gates of the memory cells, a bit line electrically connected to one ends of the memory cells through a plurality of select gate transistors, respectively, the select gate transistors including two outer select gate transistors and one or more inner select gate transistors between the two outer select gate transistors, two outer select gate lines connected to gates of the two outer select gate transistors, respectively, one or more inner select gate lines connected to gates of the one or more inner select gate transistors, respectively, and a voltage generation circuit configured to independently control supply of voltages to the outer select gate lines and the inner select gate lines during an operation to read data stored in the memory cells.
1. A semiconductor memory device comprising:
a plurality of memory cells;
a word line connected to gates of the memory cells;
a bit line electrically connected to one ends of the memory cells through a plurality of select gate transistors, respectively, the select gate transistors including two outer select gate transistors and one or more inner select gate transistors between the two outer select gate transistors;
two outer select gate lines connected to gates of the two outer select gate transistors, respectively;
one or more inner select gate lines connected to gates of the one or more inner select gate transistors, respectively; and
a voltage generation circuit configured to independently supply first voltages to the outer select gate lines and second voltages to the inner select gate lines during an operation to read data stored in the memory cells.
2. The semiconductor memory device according to claim 1 ,
wherein the voltage increase rates of the first and second voltages are controlled to be different.
3. The semiconductor memory device according to claim 2 ,
wherein the voltage generation circuit includes a first driver for outer select gate lines, that is configured to supply a voltage to the outer select gate lines, and a second driver for inner select gate lines, that is configured to supply a voltage to the inner select gate lines, and
a resistance value of a voltage supply path of the first driver is higher than a resistance value of a voltage supply path of the second driver.
4. The semiconductor memory device according to claim 1 ,
wherein application periods of overdrive voltages that are supplied to the outer select gate lines and the inner select gate lines are controlled to be different.
5. The semiconductor memory device according to claim 4 ,
wherein the voltage generation circuit includes a first voltage generation circuit for outer select gate lines, which is configured to generate a voltage that is supplied to the outer select gate lines, and a second voltage generation circuit for inner select gate lines, which is configured to generate a voltage that is supplied to the inner select gate lines, and
the application period of the overdrive voltage of the first voltage generation circuit is shorter than the application period of the second voltage generation circuit.
6. The semiconductor memory device according to claim 1 ,
wherein the voltage generation circuit includes a driver for outer select gate lines, which is configured to generate a voltage that is supplied to the outer select gate lines, and
the driver for outer select gate lines is configured to change a voltage level of the voltage supplied to the outer select gate lines depending on whether or not a memory cell that is a target to be read is connected to either of the two outer select gate transistors.
7. The semiconductor memory device according to claim 6 ,
wherein the driver for outer select gate lines decreases a resistance value of a voltage supply path if the memory cell that is a target to be read is connected to either of the two outer select gate transistors.
8. The semiconductor memory device according to claim 1 ,
wherein the voltage generation circuit includes a driver for inner select gate lines, which is configured to generate a voltage that is supplied to the inner select gate lines, and
the driver for inner select gate lines is configured to change a voltage level of the voltage supplied to the inner select gate lines depending on whether or not a memory cell that is a target to be read is connected to one of the inner select gate transistors.
9. The semiconductor memory device according to claim 8 ,
wherein the driver for inner select gate lines decreases a resistance value of a voltage supply path if the memory cell that is a target to be read is connected to one of the inner select gate transistors.
10. The semiconductor memory device according to claim 1 , wherein the first voltages include a voltage for a selected outer string unit and a voltage for a non-selected outer string unit, and the second voltages include a voltage for a selected inner string unit and a voltage for a non-selected inner string unit.
11. A method of generating voltages for a semiconductor memory device including a plurality of memory cells, a word line connected to gates of the memory cells, a bit line electrically connected to one ends of the memory cells through a plurality of select gate transistors, respectively, the select gate transistors including two outer select gate transistors and one or more inner select gate transistors between the two outer select gate transistors, two outer select gate lines connected to gates of the two outer select gate transistors, respectively, and one or more inner select gate lines connected to gates of the one or more inner select gate transistors, respectively, said method comprising:
independently supplying first voltages to the outer select gate lines and second voltages to the inner select gate lines during an operation to read data stored in the memory cells.
12. The method according to claim 11 ,
wherein the voltage increase rates of the first and second voltages are controlled to be different.
13. The method according to claim 12 , further comprising:
generating the first voltages using a first driver; and
generating the second voltages using a second driver, wherein
a resistance value of a voltage supply path of the first driver is higher than a resistance value of a voltage supply path of the second driver.
14. The method according to claim 11 ,
wherein application periods of overdrive voltages that are supplied to the outer select gate lines and the inner select gate lines are controlled to be different.
15. The method according to claim 14 ,
wherein the application period of the overdrive voltage supplied to the outer select gate lines is shorter than the application period of the overdrive voltage supplied to the inner select gate lines.
16. The method according to claim 11 , wherein the first voltages include a voltage for a selected outer string unit and a voltage for a non-selected outer string unit, and the second voltages include a voltage for a selected inner string unit and a voltage for a non-selected inner string unit.
17. The method according to claim 16 , further comprising:
changing a voltage level of the voltage for the non-selected outer string unit depending on whether or not a memory cell that is a target to be read is connected to either of the two outer select gate transistors.
18. The method according to claim 17 ,
wherein a resistance of a voltage supply path to an outer select gate line of the non-selected outer string unit is decreased if the memory cell that is a target to be read is connected to either of the two outer select gate transistors.
19. The method according to claim 11 , further comprising:
changing a voltage level of the voltage for the non-selected inner string unit depending on whether or not a memory cell that is a target to be read is connected to one of the inner select gate transistors.
20. The method according to claim 19 ,
wherein a resistance of a voltage supply path to an inner select gate line of the non-selected outer string unit is decreased if the memory cell that is a target to be read is connected to one of the inner select gate transistors.