Semiconductor device having a planar III-N semiconductor layer and fabrication method
A semiconductor device having a planar III-N semiconductor layer, comprising a substrate comprising a wafer ( 101 ) and a buffer layer ( 102 ), of a buffer material different from a material of the wafer, the buffer layer having a growth surface ( 1021 ); an array of nano structures ( 1010 ) epitaxially grown from the growth surface; a continuous planar layer ( 1020 ) formed by coalescence of upper parts of the nano structures at an elevated temperature T, wherein the number of lattice cells spanning a center distance between adjacent nano structures are different at the growth surface and at the coalesced planar layer; a growth layer ( 1030 ), epitaxially grown on the planar layer ( 1020 ).
1. A semiconductor device having a planar III-N semiconductor layer, comprising:
a substrate comprising a wafer and a buffer layer, of a different material than the wafer, having a growth surface;
an array of nanostructures epitaxially grown from the growth surface;
a continuous planar layer formed by coalescence of upper parts of the nanostructures at an elevated temperature T; and
a growth layer, epitaxially grown on the planar layer,
wherein crystal lattice spacing parallel with the growth surface is smaller in the growth layer than at the growth surface of the buffer layer,
wherein the growth layer is configured such that thermal expansion between RT and T is less for the growth layer than for the wafer, and
wherein the buffer layer has a first lattice spacing at the growth surface and the growth layer has a second lattice spacing, and wherein the coalesced planar layer has a transitional composition so that the lattice spacing of the coalesced planar layer approaches the lattice spacing of the growth layer.
2. A semiconductor device having a planar III-N semiconductor layer, comprising:
a substrate comprising a wafer and a buffer layer, of a different material than the wafer, having a growth surface;
an array of nanostructures epitaxially grown from the growth surface;
a continuous planar layer formed by coalescence of upper parts of the nanostructures at an elevated temperature T; and
a growth layer, epitaxially grown on the planar layer,
wherein crystal lattice spacing parallel with the growth surface is smaller in the growth layer than at the growth surface of the buffer layer,
wherein the growth layer is configured such that thermal expansion between RT and T is less for the growth layer than for the wafer, and
wherein the number of lattice cells spanning the distance between adjacent apertures are different at the growth surface of the buffer layer and at the coalesced planar layer.
3. A semiconductor device having a planar III-N semiconductor layer, comprising:
a substrate comprising a wafer and a buffer layer, of a different material than the wafer, having a growth surface;
an array of nanostructures epitaxially grown from the growth surface;
a continuous planar layer formed by coalescence of upper parts of the nanostructures at an elevated temperature T; and
a growth layer, epitaxially grown on the planar layer,
wherein crystal lattice spacing parallel with the growth surface is larger in the growth layer than at the growth surface of the buffer layer,
wherein the growth layer is configured such that thermal expansion between RT and T is greater for the growth layer than for the wafer, and
wherein the buffer layer has a first lattice spacing at the growth surface and the growth layer has a second lattice spacing, and wherein the coalesced planar layer has a transitional composition so that the lattice spacing of the coalesced planar layer approaches the lattice spacing of the growth layer.
4. A semiconductor device having a planar III-N semiconductor layer, comprising:
a substrate comprising a wafer and a buffer layer, of a different material than the wafer, having a growth surface;
an array of nanostructures epitaxially grown from the growth surface;
a continuous planar layer formed by coalescence of upper parts of the nanostructures at an elevated temperature T; and
a growth layer, epitaxially grown on the planar layer,
wherein crystal lattice spacing parallel with the growth surface is larger in the growth layer than at the growth surface of the buffer layer,
wherein the growth layer is configured such that thermal expansion between RT and T is greater for the growth layer than for the wafer, and
wherein the number of lattice cells spanning the distance between adjacent apertures are different at the growth surface of the buffer layer and at the coalesced planar layer.
5. The semiconductor device of claim 4 , wherein the coalesced planar layer ( 1020 ) has a mean lattice spacing corresponding to it being formed at the elevated temperature, T, with the nominal lattice spacing of an essentially relaxed III-N crystal of the buffer layer material.