IP Library Granted Patent US 11,393,897
Granted Patent B2
US 11,393,897 · App. 17/202,301 · Granted Jul 19, 2022

Capacitor structures for memory and method of manufacturing the same

Inventor: Kai-Jyun Huang (Hsinchu, TW)
Assignee: Powerchip Semiconductor Manufacturing Corporation
H01L28/92H01L27/10808H01L27/10852
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Quick Facts
Patent No.
US 11,393,897
App. No.
17/202,301
Granted
Jul 19, 2022
Kind
B2
Abstract

A capacitor structure of memory is provided in the present invention, including structures of multiple cylindrical bottom electrode layers with bottoms contacting a substrate and extending vertically and upwardly from the substrate, the cylindrical shape of the bottom electrode layer has a sidewall with wavelike cross-section, and the wavelike cross-sections of adjacent bottom electrode layers are identical but shifted vertically by a distance, a capacitive dielectric layer on the bottom electrode layers, and a top electrode layer on the capacitive dielectric layer.

Claims (9)

1. A capacitor structure of memory, comprising:

a substrate;

multiple cylindrical bottom electrode layers, wherein a bottom of each said bottom electrode layer contacts said substrate and extends vertically and upwardly from said substrate, and said cylindrical bottom electrode layer has a sidewall with wavelike cross-section, and said wavelike cross-sections of each said cylindrical bottom electrode layer is shifted vertically by a distance from said wavelike cross-section of adjacent said cylindrical bottom electrode layer;

a capacitive dielectric layer on said bottom electrode layers; and

a top electrode layer on said capacitive dielectric layer.

2. The capacitor structure of memory of claim 1 , wherein said wavelike cross-section is made up of multiple continuous arcs, and said arcs in said wavelike cross-section of each said bottom electrode layer have at least two different lengths and at least two different radians.

3. The capacitor structure of memory of claim 1 , further comprising a conductive layer on said top electrode layer.

4. The capacitor structure of memory of claim 1 , further comprising supporting structures between adjacent said bottom electrode layers and connecting said adjacent bottom electrode layers.

5. The capacitor structure of memory of claim 4 , wherein each said supporting structure comprises a hard mask layer connecting top ends of said adjacent bottom electrode layers.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 15, 2021
From: HUANG, KAI-JYUN
To: POWERCHIP SEMICONDUCTOR MANUFACTURING CORPORATION
Reel/Frame 055598/0251 →
Priority Claims (1)
TW 109139096 · Nov 10, 2020 · national
Continuity (1)
Related Publication 20220149149A1 · May 12, 2022