Method, circuit, and SOC for performing matrix multiplication operation
A method for performing a matrix multiplication operation is provided. The method includes: obtaining a matrix B 1 , a matrix A 2 , and an index matrix, wherein the index matrix comprises indexes, in a matrix A 1 , of elements in the matrix A 2 ; generating m matrices B 2 based on the index matrix and the matrix B 1 , wherein the m matrices B 2 are all matrices with t rows and n columns, and each row of each matrix B 2 is a row indicated in the matrix B 1 by a corresponding element in the index matrix; and generating a matrix C based on the matrix A 2 and the m matrices B 2 , wherein the matrix C is a product of the matrix A 1 and the matrix B 1.
1. A method for performing a matrix multiplication operation, comprising:
obtaining, by a multiplication circuitry, a matrix B 1 having k rows and n columns, a matrix A 2 having m rows and t columns, and an index matrix having m rows and t columns, wherein the matrix A 2 includes a plurality of elements that were selected from a matrix A 1 having m rows and k columns, wherein the index matrix is based on a selection of the plurality of elements of the matrix A 2 and comprises a plurality of indexes indicating locations within the matrix A 1 from which the plurality of elements of the matrix A 2 were selected, wherein k, n, m, and t are all positive integers, and t is less than or equal to k;
selecting, by the multiplication circuitry, elements corresponding to the indexes of the index matrix from the matrix B 1 ; and
performing, by the multiplication circuitry, the matrix multiplication operation based on the matrix A 2 and the selected elements from the matrix B 1 .
2. The method according to claim 1 , further comprising:
generating, by the multiplication circuitry, a matrix C based on the elements of the matrix A 2 and the elements selected from the matrix B 1 , wherein the matrix C includes m rows and n columns.
3. The method according to claim 1 , wherein the obtaining the matrix A 2 comprises:
generating the matrix A 2 based on the matrix A 1 , wherein the m rows of the matrix A 2 are in a one-to-one correspondence with the m rows of the matrix A 1 in sequence, and elements in each row of the matrix A 2 comprise all non-zero elements in groups that are sequentially arranged in a corresponding row of the matrix A 1 .
4. The method according to claim 1 , wherein the matrix A 1 is a parameter matrix of a trained neural network.
5. The method according to claim 1 , wherein the obtaining the index matrix comprises:
generating the index matrix based on the matrix A 1 , wherein the m rows of the index matrix are in a one-to-one correspondence with the m rows of the matrix A 2 in sequence, and elements in each row of the index matrix are column indexes of all elements that are sequentially arranged in a corresponding row of the matrix A 2 .
6. The method according to claim 1 , wherein the matrix A 2 comprises all non-zero elements in the matrix A 1 , and the index matrix comprises indexes of all non-zero elements in the matrix A 1 .
7. The method according to claim 1 , wherein the matrix A 1 is a conditional sparsity matrix.
8. The method according to claim 7 , wherein elements in each of the m rows of the matrix A 1 are grouped into at least one group, a quantity of elements in each group is the same, and a quantity of non-zero elements in each group is the same.
9. The method according to claim 8 , wherein the quantity of elements in each group is 4 and the quantity of non-zero elements in each group is 2.
10. A circuitry for performing a matrix multiplication operation, comprising:
an obtaining circuit configured to obtain a matrix B 1 having k rows and n columns, a matrix A 2 having m rows and t columns, and an index matrix having m rows and t columns, wherein the matrix A 2 includes a plurality of elements that were selected from a matrix A 1 having m rows and k columns, wherein the index matrix is based on a selection of the plurality of elements of the matrix A 2 and comprises a plurality of indexes indicating locations within the matrix A 1 from which the plurality of elements of the matrix A 2 were selected, wherein k, n, m, and t are all positive integers, and t is less than or equal to k;
a data selection circuit configured to select elements corresponding to the indexes of the index matrix from the matrix B 1 ; and
a multiplication circuit configured to perform the matrix multiplication operation based on the matrix A 2 and the selected elements from the matrix B 1 .
11. The circuitry according to claim 10 , further comprising:
a computing unit array configured to generate a matrix C based on the elements of the matrix A 2 and the elements selected from the matrix B 1 by the data selection circuit, wherein the matrix C includes m rows and n columns.
12. The circuitry according to claim 10 , wherein the m rows of the matrix A 2 are in a one-to-one correspondence with the m rows of the matrix A 1 in sequence, and elements in each row of the matrix A 2 comprise all non-zero elements in groups that are sequentially arranged in a corresponding row of the matrix A 1 .
13. The circuitry according to claim 10 , wherein the matrix A 1 is a parameter matrix of a trained neural network.
14. The circuitry according to claim 10 , wherein the circuitry further comprises a first memory configured to store the matrix B 1 , the matrix A 2 , and the index matrix;
wherein the obtaining circuit is configured to read the matrix B 1 , the matrix A 2 , and the index matrix from the first memory.
15. The circuitry according to claim 10 , wherein the m rows of the index matrix are in a one-to-one correspondence with the m rows of the matrix A 2 in sequence, and elements in each row of the index matrix are column indexes, in the matrix A 1 , of all elements that are sequentially arranged in a corresponding row of the matrix A 2 .
16. The circuitry according to claim 10 , wherein the matrix A 2 comprises all non-zero elements in the matrix A 1 , and the index matrix comprises indexes of all non-zero elements in the matrix A 1 .
17. The circuitry according to claim 10 , wherein the matrix A 1 is a conditional sparsity matrix.
18. The circuitry according to claim 17 , wherein elements in each of the m rows of the matrix A 1 are grouped into at least one group, a quantity of elements in each group is the same, and a quantity of non-zero elements in each group is the same.
19. The circuitry according to claim 18 , wherein the quantity of elements in each group is 4 and the quantity of non-zero elements in each group is 2.
20. A system on chip (SOC), comprising:
a circuitry; and
a processing core configured to control the circuitry to perform a matrix multiplication operation, wherein the circuitry comprises:
an obtaining circuit configured to obtain a matrix B 1 having k rows and n columns, a matrix A 2 having m rows and t columns, and an index matrix having m rows and t columns, wherein the matrix A 2 includes a plurality of elements that were selected from a matrix A 1 having m rows and k columns, wherein the index matrix is based on a selection of the plurality of elements of the matrix A 2 and comprises a plurality of indexes indicating locations within the matrix A 1 from which the plurality of elements of the matrix A 2 were selected, wherein k, n, m, and t are all positive integers, and t is less than or equal to k;
a data selection circuit configured to select elements corresponding to the indexes of the index matrix from the matrix B 1 ; and
a multiplication circuit configured to perform the matrix multiplication operation based on the matrix A 2 and the selected elements from the matrix B 1 .
21. The SOC according to claim 20 , the circuitry further comprising:
a computing unit array configured to generate a matrix C based on the elements of the matrix A 2 and the elements selected from the matrix B 1 by the data selection circuit, wherein the matrix C includes m rows and n columns.
22. A device, comprising:
a circuitry;
a semiconductor medium storing an instruction; and
a processing core configured to run the instruction to control the circuitry to perform a matrix multiplication operation, wherein the circuitry comprises:
an obtaining circuit configured to obtain a matrix B 1 having k rows and n columns, a matrix A 2 having m rows and t columns, and an index matrix having m rows and t columns, wherein the matrix A 2 includes a plurality of elements that were selected from a matrix A 1 having m rows and k columns, wherein the index matrix is based on a selection of the plurality of elements of the matrix A 2 and comprises a plurality of indexes indicating locations within the matrix A 1 from which the plurality of elements of the matrix A 2 were selected, wherein k, n, m, and t are all positive integers, and t is less than or equal to k;
a data selection circuit configured to select elements corresponding to the indexes of the index matrix from the matrix B 1 ; and
a multiplication circuit configured to perform the matrix multiplication operation based on the matrix A 2 and the selected elements from the matrix B 1 .
23. The device according to claim 22 , the circuitry further comprising:
a computing unit array configured to generate a matrix C based on the elements of the matrix A 2 and the elements selected from the matrix B 1 by the data selection circuit, wherein the matrix C includes m rows and n columns.